From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 23:21:10 +0000 (-0700)
Subject: Keep track of bits in variable length chain, to check for taps
X-Git-Tag: working-ls180~1085^2~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83e2d87fb80cc5aed018b0f3409f256ef7f7b385;p=yosys.git

Keep track of bits in variable length chain, to check for taps
---

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index fcfa79ea6..d17799208 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -186,6 +186,11 @@ state <int> shiftx_width
 state <int> slice
 udata <int> minlen
 udata <vector<pair<Cell*,int>>> chain
+udata <pool<SigBit>> chain_bits
+
+code
+	chain_bits.clear();
+endcode
 
 match shiftx
 	select shiftx->type.in($shiftx)
@@ -251,13 +256,20 @@ match next
 	index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
 	filter port(next, clk_port) == port(first, clk_port)
 	filter en_port == IdString() || port(next, en_port) == port(first, en_port)
+	filter !chain_bits.count(port(next, \D)[idx])
 	set slice idx
 endmatch
 
 code
 	if (next) {
+		chain_bits.insert(port(next, \Q)[slice]);
 		chain.emplace_back(next, slice);
 		if (GetSize(chain) < shiftx_width)
 			subpattern(tail);
 	}
+finally
+	if (next) {
+		chain_bits.erase(port(next, \Q)[slice]);
+		chain.pop_back();
+	}
 endcode