From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 Jun 2018 13:24:11 +0000 (+0100)
Subject: add cell outen wires
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83edefe97d77ec6faeb2331337baecfe842f34c9;p=pinmux.git

add cell outen wires
---

diff --git a/src/test_bsv/pinmux.bsv b/src/test_bsv/pinmux.bsv
index 7962109..2fea0b5 100644
--- a/src/test_bsv/pinmux.bsv
+++ b/src/test_bsv/pinmux.bsv
@@ -88,17 +88,20 @@ package pinmux;
       Wire#(Bit#(1)) wrcell2_mux<-mkDWire(0);
       // following wires capture signals to IO CELL if io-0 is
       // allotted to it
-      GenericIOType cell0_mux_out=unpack(0);
+      Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0);
+      Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0);
       Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0);
 
       // following wires capture signals to IO CELL if io-1 is
       // allotted to it
-      GenericIOType cell1_mux_out=unpack(0);
+      Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0);
+      Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0);
       Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0);
 
       // following wires capture signals to IO CELL if io-2 is
       // allotted to it
-      GenericIOType cell2_mux_out=unpack(0);
+      Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0);
+      Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0);
       Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0);
 
       // following wires capture signals to IO CELL if uart-0 is
@@ -225,6 +228,14 @@ package pinmux;
 			wrcell2_mux==1?0:
 			twi0_scl_io;
 
+      // TODO: here is needed something which sets a new
+      // wire, cell2_mux_outen
+      cell2_mux_outen=
+            wrcell2_mux==0?gpioa_a2_io.output_en:
+			wrcell2_mux==1?0:
+			twi0_scl_io.output_en;
+
+
       rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0);
         wrgpioa_a2_in<=cell2_mux_in;
       endrule