From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 12 Jul 2019 23:06:14 +0000 (-0700)
Subject: Cleanup
X-Git-Tag: working-ls180~1190^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83f23a24a880fb3cd40ea16b478540bdbdfe597c;p=yosys.git

Cleanup
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 5da5efcdc..867b06cbe 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -611,21 +611,15 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 								RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
 								RTLIL::Const::from_string("01"));
 						bit2sinks[cell->getPort("\\A")].push_back(cell);
+						cell_stats["$lut"]++;
 					}
-					else {
+					else
 						push_inverters.emplace_back(c, driver_lut);
-						continue;
-					}
+					continue;
 				}
-				else {
-					cell = module->addCell(remap_name(c->name), "$_NOT_");
-					cell->setPort("\\A", RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset));
-					cell->setPort("\\Y", RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset));
-					cell_stats[RTLIL::unescape_id(c->type)]++;
+				else
 					log_abort();
-				}
 				if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
-				cell_stats[RTLIL::unescape_id(c->type)]++;
 				continue;
 			}
 			cell_stats[RTLIL::unescape_id(c->type)]++;