From: Ilya Epifanov Date: Tue, 28 Apr 2020 20:13:53 +0000 (+0200) Subject: Added `imac` config for CPUs which implements the most basic working riscv32imac... X-Git-Tag: 24jan2021_ls180~365^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83f4dcb2c6950e33a32f08abc61aed3abc9b6e1b;p=litex.git Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv --- diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py index 21f7ce5d..5497bac8 100644 --- a/litex/soc/cores/cpu/__init__.py +++ b/litex/soc/cores/cpu/__init__.py @@ -61,6 +61,7 @@ CPU_VARIANTS = { "minimal" : ["min",], "lite" : ["light", "zephyr", "nuttx"], "standard": [None, "std"], + "imac": [], "full": [], "linux" : [], "linuxd" : [], diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 8e27e5d3..1ed0494b 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -25,6 +25,8 @@ CPU_VARIANTS = { "lite+debug": "VexRiscv_LiteDebug", "standard": "VexRiscv", "standard+debug": "VexRiscv_Debug", + "imac": "VexRiscv_IMAC", + "imac+debug": "VexRiscv_IMACDebug", "full": "VexRiscv_Full", "full+debug": "VexRiscv_FullDebug", "linux": "VexRiscv_Linux", @@ -47,6 +49,8 @@ GCC_FLAGS = { "lite+debug": "-march=rv32i -mabi=ilp32", "standard": "-march=rv32im -mabi=ilp32", "standard+debug": "-march=rv32im -mabi=ilp32", + "imac": "-march=rv32imac -mabi=ilp32", + "imac+debug": "-march=rv32imac -mabi=ilp32", "full": "-march=rv32im -mabi=ilp32", "full+debug": "-march=rv32im -mabi=ilp32", "linux": "-march=rv32ima -mabi=ilp32",