From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 2 Feb 2014 20:09:08 +0000 (+0100)
Subject: Added constant-clock case to opt_rmdff
X-Git-Tag: yosys-0.2.0~113
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83fa65282017cb39a31c6c4c878b9960d8097b66;p=yosys.git

Added constant-clock case to opt_rmdff
---

diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 9ce98004e..a8e2c4121 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -92,6 +92,14 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		}
 	}
 
+	if (sig_c.is_fully_const()) {
+		if (val_rv.bits.size() == 0)
+			val_rv = RTLIL::Const(RTLIL::State::Sx, sig_q.width);
+		RTLIL::SigSig conn(sig_q, val_rv);
+		mod->connections.push_back(conn);
+		goto delete_dff;
+	}
+
 	if (sig_d.is_fully_undef() && sig_d.width == int(val_rv.bits.size())) {
 		RTLIL::SigSig conn(sig_q, val_rv);
 		mod->connections.push_back(conn);