From: Andrew Cagney Date: Thu, 21 May 1998 08:18:21 +0000 (+0000) Subject: * interp.c (sim_fetch_register): Convert internal r5900 regs to X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84048259930b9dc812404285e3508eb09beeec51;p=binutils-gdb.git * interp.c (sim_fetch_register): Convert internal r5900 regs to target byte order --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 7900ebabb6d..2afcd498cea 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,10 @@ +start-sanitize-r5900 +Thu May 21 17:15:39 1998 Andrew Cagney + + * interp.c (sim_fetch_register): Convert internal r5900 regs to + target byte order + +end-sanitize-r5900 Mon May 18 18:22:42 1998 Frank Ch. Eigler * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware @@ -35,11 +42,13 @@ Wed May 13 14:27:53 1998 Gavin Koch function check_op_hilo_hi1lo1 with the pair check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1. +start-sanitize-r5900 Wed May 13 14:11:46 1998 Gavin Koch * tx.igen (madd,maddu): Replace calls to check_op_hilo with calls to check_div_hilo. +end-sanitize-r5900 Wed May 13 09:59:27 1998 Gavin Koch * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): diff --git a/sim/mips/interp.c b/sim/mips/interp.c index f83fdc3a31b..e0c878d6763 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -1017,7 +1017,7 @@ sim_fetch_register (sd,rn,memory,length) /* start-sanitize-r5900 */ if (rn >= 90 && rn < 90 + 32) { - *(unsigned64*)memory = GPR1[rn - 90]; + *((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]); return 8; } switch (rn)