From: Steve Reinhardt <stever@gmail.com>
Date: Mon, 11 Jan 2016 21:20:38 +0000 (-0500)
Subject: mem: fix bug in packet access endianness changes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8406a54907a00e19389389f0b1497164a7bc637d;p=gem5.git

mem: fix bug in packet access endianness changes

The new Packet::setRaw() method incorrectly still contained
an htog() conversion.  As a result, calls to the old set()
method (now defined as setRaw(htog(v))) underwent two htog
conversions, which breaks things when htog() is not a no-op.

Interestingly the only test that caught this was a SPARC
boot test, where an IsaFake device with a non-zero return
value was getting swapped twice resulting in a register
getting loaded with 0x100000000000000 instead of 1.
(Good reason for keeping SPARC around, perhaps?)
---

diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh
index 1a2db6921..1fee979ce 100644
--- a/src/mem/packet_access.hh
+++ b/src/mem/packet_access.hh
@@ -66,7 +66,7 @@ Packet::setRaw(T v)
 {
     assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA));
     assert(sizeof(T) <= size);
-    *(T*)data = TheISA::htog(v);
+    *(T*)data = v;
 }