From: Kyrylo Tkachov Date: Tue, 21 Apr 2015 11:24:05 +0000 (+0000) Subject: [AArch64] Add zero_extend variants of logical+not ops X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8409e468a5f94b7577ccfa073f8b859481a86800;p=gcc.git [AArch64] Add zero_extend variants of logical+not ops * config/aarch64/aarch64.md (*_one_cmplsidi3_ze): New pattern. (*xor_one_cmplsidi3_ze): Likewise. From-SVN: r222263 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 73ede9eada0..2a982b1bd7f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-04-21 Kyrylo Tkachov + + * config/aarch64/aarch64.md (*_one_cmplsidi3_ze): + New pattern. + (*xor_one_cmplsidi3_ze): Likewise. + 2015-04-21 Thomas Preud'homme * df-core.c (df_finish_pass): Iterate over df->problems_by_index[] and diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 534a862b4ad..429c5bac000 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3058,6 +3058,26 @@ (set_attr "simd" "*,yes")] ) +(define_insn "*_one_cmplsidi3_ze" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (NLOGICAL:SI (not:SI (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "r"))))] + "" + "\\t%w0, %w2, %w1" + [(set_attr "type" "logic_reg")] +) + +(define_insn "*xor_one_cmplsidi3_ze" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (not:SI (xor:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")))))] + "" + "eon\\t%w0, %w1, %w2" + [(set_attr "type" "logic_reg")] +) + ;; (xor (not a) b) is simplify_rtx-ed down to (not (xor a b)). ;; eon does not operate on SIMD registers so the vector variant must be split. (define_insn_and_split "*xor_one_cmpl3"