From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 10 Oct 2022 16:31:17 +0000 (+0100)
Subject: shorten wording
X-Git-Tag: opf_rfc_ls005_v1~100
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8413bdd1303771c2c776a8e2f24790e7e08bd3c2;p=libreriscv.git

shorten wording
---

diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index aafcac9a0..dca0fb6a9 100644
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -60,10 +60,10 @@
 
 **Motivation**
 
-Similar to `lxvkq` but extended to a full bfloat16 with one
+Similar to `lxvkq` but extended to a bfloat16 with one
 32-bit instruction and a full FP32 in two 32-bit instructions
 these instructions always save a Data Load and associated L1
-and TLB lookup. Even quickly clearing an FPR to zero presently requires Load.
+and TLB lookup. Even quickly clearing an FPR to zero presently needs Load.
 
 **Notes and Observations**: