From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 23:41:34 +0000 (-0800)
Subject: Brackets
X-Git-Tag: working-ls180~881^2^2~124^2~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84153288bb7d92c31c1d8873b1257a296ca664ad;p=yosys.git

Brackets
---

diff --git a/passes/techmap/clkpart.cc b/passes/techmap/clkpart.cc
index 4fa729250..bf3b5bd30 100644
--- a/passes/techmap/clkpart.cc
+++ b/passes/techmap/clkpart.cc
@@ -144,7 +144,7 @@ struct ClkPartPass : public Pass {
 				{
 					bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
 					bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
-					key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E)) : RTLIL::SigSpec()));
+					key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec());
 				}
 				else
 					continue;