From: R Veera Kumar <vklr@vkten.in>
Date: Mon, 22 Nov 2021 02:34:26 +0000 (+0530)
Subject: Add expected state to case_addme_ca_so_4 in alu_cases unit test
X-Git-Tag: sv_maxu_works-initial~720
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8416f2d77f045b386ca280214cbe3a7ea07082bc;p=openpower-isa.git

Add expected state to case_addme_ca_so_4 in alu_cases unit test
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index 71e45c2f..bcf34a0f 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -145,8 +145,13 @@ class ALUTestCase(TestAccumulatorBase):
         xer = SelectableInt(0, 64)
         xer[XER_bits['CA']] = 1
         initial_sprs[special_sprs['XER']] = xer
+        e = ExpectedState(pc=4)
+        e.intregs[16] = 0x7fffffffffffffff
+        e.intregs[6] = 0x7fffffffffffffff
+        e.ca = 0x3
+        e.crregs[0] = 0x4
         self.add_case(Program(lst, bigendian),
-                      initial_regs, initial_sprs)
+                      initial_regs, initial_sprs, expected=e)
 
     def case_addme_ca_so_3(self):
         """bug where SO does not get passed through to CR0