From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 27 Nov 2014 14:12:05 +0000 (+0800)
Subject: minicon: remove unused signals and fix indent
X-Git-Tag: 24jan2021_ls180~2621
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8418ccafdccf6d61f056d72440e046d97be0528d;p=litex.git

minicon: remove unused signals and fix indent
---

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
index d605a1a6..7d63ee4e 100644
--- a/misoclib/gensoc/__init__.py
+++ b/misoclib/gensoc/__init__.py
@@ -177,7 +177,6 @@ class SDRAMSoC(GenSoC):
 			self.add_cpu_memory_region("sdram", 0x40000000,
 				2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8)
 		elif self.ramcon_type == "minicon":
-			rdphase = phy_settings.rdphase
 			self.submodules.minicon = sdramcon = Minicon(phy_settings, sdram_geom, sdram_timing)
 			self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave)
 			sdram_width = flen(sdramcon.bus.dat_r)
diff --git a/misoclib/sdram/minicon/__init__.py b/misoclib/sdram/minicon/__init__.py
index 6cd36744..a90f1571 100755
--- a/misoclib/sdram/minicon/__init__.py
+++ b/misoclib/sdram/minicon/__init__.py
@@ -57,7 +57,6 @@ class Minicon(Module):
 
 		self.bus = bus = wishbone.Interface(data_width=phy_settings.nphases*flen(dfi.phases[rdphase].rddata))
 		slicer = _AddressSlicer(geom_settings.col_a, geom_settings.bank_a, geom_settings.row_a, address_align)
-		req_addr = Signal(geom_settings.col_a + geom_settings.bank_a + geom_settings.row_a)
 		refresh_req = Signal()
 		refresh_ack = Signal()
 		wb_access = Signal()
@@ -67,7 +66,6 @@ class Minicon(Module):
 		row_closeall = Signal()
 		addr_sel = Signal(max=3, reset=A10_ENABLED)
 		has_curbank_openrow = Signal()
-		cl_counter = Signal(max=phy_settings.cl+1)
 
 		# Extra bit means row is active when asserted
 		self.openrow = openrow = Array(Signal(geom_settings.row_a + 1) for b in nbanks)
@@ -122,19 +120,19 @@ class Minicon(Module):
 			If(refresh_req,
 				NextState("PRECHARGEALL")
 			).Elif(wb_access,
-                                If(hit & bus.we,
-                                        NextState("WRITE"),
-                                ),
-                                If(hit & ~bus.we,
-                                        NextState("READ"),
-                                ),
-                                If(has_curbank_openrow & ~hit,
-                                        NextState("PRECHARGE")
-                                ),
-                                If(~has_curbank_openrow,
-                                        NextState("ACTIVATE")
-                                ),
-                        )
+				If(hit & bus.we,
+						NextState("WRITE"),
+				),
+				If(hit & ~bus.we,
+						NextState("READ"),
+				),
+				If(has_curbank_openrow & ~hit,
+						NextState("PRECHARGE")
+				),
+				If(~has_curbank_openrow,
+						NextState("ACTIVATE")
+				),
+			)
 		)
 		fsm.act("READ",
 			# We output Column bits at address pins so that A10 is 0