From: Rhys Perry Date: Mon, 25 May 2020 13:49:53 +0000 (+0100) Subject: radv/aco,aco: allow SMEM SSBO loads on GFX6/7 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=841fdfcd4537d826b2b49b927fadb7a32f0b2286;p=mesa.git radv/aco,aco: allow SMEM SSBO loads on GFX6/7 Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 6a35c3188c4..f879a81c6ce 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -5145,7 +5145,7 @@ void load_buffer(isel_context *ctx, unsigned num_components, unsigned component_ { Builder bld(ctx->program, ctx->block); - bool use_smem = dst.type() != RegType::vgpr && (ctx->options->chip_class >= GFX8 || readonly) && allow_smem; + bool use_smem = dst.type() != RegType::vgpr && (!glc || ctx->options->chip_class >= GFX8) && allow_smem; if (use_smem) offset = bld.as_uniform(offset); diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index dbba3d155b4..d60cd69445d 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -348,7 +348,7 @@ void fill_desc_set_info(isel_context *ctx, nir_function_impl *impl) bool glc = access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE); switch (intrin->intrinsic) { case nir_intrinsic_load_ssbo: { - if (nir_dest_is_divergent(intrin->dest) || ctx->program->chip_class < GFX8) + if (nir_dest_is_divergent(intrin->dest) && (!glc || ctx->program->chip_class >= GFX8)) flags |= glc ? has_glc_vmem_load : has_nonglc_vmem_load; res = intrin->src[0].ssa; break; diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 670de040d38..afc90b74f7d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2953,8 +2953,7 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, flush_bits |= RADV_CMD_FLAG_INV_VCACHE; /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to * invalidate the scalar cache. */ - if (cmd_buffer->device->physical_device->use_aco && - cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) + if (cmd_buffer->device->physical_device->use_aco) flush_bits |= RADV_CMD_FLAG_INV_SCACHE; if (!image_is_coherent)