From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 21:56:19 +0000 (-0700)
Subject: Use built-in async2sync call as per #1417
X-Git-Tag: working-ls180~990^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8422ad3e3a5db583f59906f8a5d81587dd777f6d;p=yosys.git

Use built-in async2sync call as per #1417
---

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 1f643cb4e..795ac9074 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -4,11 +4,7 @@ design -save read
 proc
 async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
 flatten
-synth_xilinx
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-design -load read
 
 synth_xilinx
 flatten