From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 23 Jun 2021 15:07:12 +0000 (+0100)
Subject: better ways to do sign-inversion (without multiply which rounds)
X-Git-Tag: xlen-bcd~413
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84253e7b6f4da7b9588de1b31d7c29313ef2d5fa;p=openpower-isa.git

better ways to do sign-inversion (without multiply which rounds)
also fix FP unit tests
---

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index ead78759..6b270a96 100644
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -276,12 +276,21 @@ def FPSUB32(FRA, FRB):
     return cvt
 
 
+def signinv(res, sign):
+    if sign == 1:
+        return res
+    if sign == 0:
+        return 0.0
+    if sign == -1:
+        return -res
+
+
 def FPMUL32(FRA, FRB, sign=1):
     from openpower.decoder.isafunctions.double2single import DOUBLE2SINGLE
     #return FPMUL64(FRA, FRB)
-    #FRA = DOUBLE(SINGLE(FRA))
-    #FRB = DOUBLE(SINGLE(FRB))
-    result = float(FRA) * float(FRB) * float(sign)
+    FRA = DOUBLE(SINGLE(FRA))
+    FRB = DOUBLE(SINGLE(FRB))
+    result = signinv(float(FRA) * float(FRB), sign)
     log ("FPMUL32", FRA, FRB, float(FRA), float(FRB), result, sign)
     cvt = fp64toselectable(result)
     cvt = DOUBLE2SINGLE(cvt)
@@ -320,7 +329,7 @@ def FPDIV32(FRA, FRB, sign=1):
     #return FPDIV64(FRA, FRB)
     #FRA = DOUBLE(SINGLE(FRA))
     #FRB = DOUBLE(SINGLE(FRB))
-    result = float(sign) * float(FRA) / float(FRB)
+    result = signinv(float(FRA) / float(FRB), sign)
     cvt = fp64toselectable(result)
     cvt = DOUBLE2SINGLE(cvt)
     log ("FPDIV32", FRA, FRB, result, cvt)
@@ -342,14 +351,14 @@ def FPSUB64(FRA, FRB):
 
 
 def FPMUL64(FRA, FRB, sign=1):
-    result = float(FRA) * float(FRB) * float(sign)
+    result = signinv(float(FRA) * float(FRB), sign)
     cvt = fp64toselectable(result)
     log ("FPMUL64", FRA, FRB, result, cvt, sign)
     return cvt
 
 
 def FPDIV64(FRA, FRB, sign=1):
-    result = float(sign) * float(FRA) / float(FRB)
+    result = signinv(float(FRA) / float(FRB), sign)
     cvt = fp64toselectable(result)
     log ("FPDIV64", FRA, FRB, result, cvt, sign)
     return cvt
diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index cc87701a..615ff5d5 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -224,7 +224,7 @@ class DecoderTestCase(FHDLTestCase):
 
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_fprs=fprs)
-            self.assertEqual(sim.fpr(3), SelectableInt(0x3d9d8b31c0000000, 64))
+            self.assertEqual(sim.fpr(3), SelectableInt(0x3d8b1663a0000000, 64))
 
     def test_fp_muls4(self):
         """>>> lst = ["fmuls 3, 1, 2",