From: lkcl <lkcl@web>
Date: Tue, 3 Aug 2021 23:58:50 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~514
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8438c70787931b52f4a607f000185ac974db0ba2;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 7f7295bef..0cee13c33 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -109,6 +109,14 @@ Note that whilst it is possible to set both MVL and VL from the same
 immediate, it is not possible to set them to different immediates in
 the same instruction.  That would require two instructions.
 
+# setmvlhi
+
+Form: SVL-Form (see [[isatables/fields.text]])
+
+| 0.5|6.10|11.15|16..21|22| 23...25  | 26.30 |31|  name   |
+| -- | -- | --- | ---- |--| -------- | ----- |--| ------- |
+|OPCD| RT | RA  | SVi  |/ | ms vs vf | 11110 |Rc| setvl   |
+
 # Vertical First Mode
 
 Vertical First is effectively like an implicit single bit predicate