From: Michael Neuling <mikey@neuling.org>
Date: Mon, 17 May 2021 06:19:47 +0000 (+1000)
Subject: Merge pull request #277 from paulus/gpio
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84473eda1b54a03794b2f3d13748f42b52ead34e;p=microwatt.git

Merge pull request #277 from paulus/gpio

A few cleanups. GPIO IRQ number is now 4 as 3 is now taken by the SD card.
---

84473eda1b54a03794b2f3d13748f42b52ead34e
diff --cc Makefile
index 2d34627,05eff4a..1b1f714
--- a/Makefile
+++ b/Makefile
@@@ -53,8 -50,8 +53,8 @@@ core_files = decode_types.vhdl common.v
  	loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \
  	core.vhdl fpu.vhdl
  
 -soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
 +soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
- 	wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \
+ 	wishbone_debug_master.vhdl xics.vhdl syscon.vhdl gpio.vhdl soc.vhdl \
  	spi_rxtx.vhdl spi_flash_ctrl.vhdl
  
  uart_files = $(wildcard uart16550/*.v)
diff --cc fpga/top-arty.vhdl
index cb7f781,e36f05d..8e6ff02
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@@ -27,7 -27,7 +27,8 @@@ entity toplevel i
          USE_LITEETH        : boolean  := false;
          UART_IS_16550      : boolean  := false;
          HAS_UART1          : boolean  := true;
-         USE_LITESDCARD     : boolean := false
++        USE_LITESDCARD     : boolean := false;
+         NGPIO              : natural := 32
          );
      port(
          ext_clk   : in  std_ulogic;
@@@ -202,8 -187,8 +205,9 @@@ begi
              LOG_LENGTH         => LOG_LENGTH,
              HAS_LITEETH        => USE_LITEETH,
              UART0_IS_16550     => UART_IS_16550,
 -            HAS_UART1          => false,
 +            HAS_UART1          => HAS_UART1,
-             HAS_SD_CARD        => USE_LITESDCARD
++            HAS_SD_CARD        => USE_LITESDCARD,
+             NGPIO              => NGPIO
              )
          port map (
              -- System signals
@@@ -225,9 -210,13 +229,14 @@@
              spi_flash_sdat_oe => spi_sdat_oe,
              spi_flash_sdat_i  => spi_sdat_i,
  
+             -- GPIO signals
+             gpio_in           => gpio_in,
+             gpio_out          => gpio_out,
+             gpio_dir          => gpio_dir,
+ 
              -- External interrupts
              ext_irq_eth       => ext_irq_eth,
 +            ext_irq_sdcard    => ext_irq_sdcard,
  
              -- DRAM wishbone
              wb_dram_in           => wb_dram_in,
diff --cc soc.vhdl
index cee4753,2bf3b72..8c0401a
--- a/soc.vhdl
+++ b/soc.vhdl
@@@ -46,8 -46,6 +47,9 @@@ use work.wishbone_types.all
  --
  --   0  : UART0
  --   1  : Ethernet
 +--   2  : UART1
 +--   3  : SD card
++--   4  : GPIO
  
  entity soc is
      generic (
@@@ -71,14 -68,7 +73,15 @@@
          HAS_LITEETH        : boolean := false;
  	UART0_IS_16550     : boolean := true;
  	HAS_UART1          : boolean := false;
 +        ICACHE_NUM_LINES   : natural := 64;
 +        ICACHE_NUM_WAYS    : natural := 2;
 +        ICACHE_TLB_SIZE    : natural := 64;
 +        DCACHE_NUM_LINES   : natural := 64;
 +        DCACHE_NUM_WAYS    : natural := 2;
 +        DCACHE_TLB_SET_SIZE : natural := 64;
 +        DCACHE_TLB_NUM_WAYS : natural := 2;
-         HAS_SD_CARD        : boolean := false
++        HAS_SD_CARD        : boolean := false;
+         NGPIO              : natural := 0
  	);
      port(
  	rst          : in  std_ulogic;
@@@ -897,7 -855,7 +935,8 @@@ begi
          int_level_in(0) <= uart0_irq;
          int_level_in(1) <= ext_irq_eth;
          int_level_in(2) <= uart1_irq;
 -        int_level_in(3) <= gpio_intr;
 +        int_level_in(3) <= ext_irq_sdcard;
++        int_level_in(4) <= gpio_intr;
      end process;
  
      -- BRAM Memory slave