From: lkcl Date: Tue, 19 Apr 2022 13:11:35 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2699 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8454d0fb969f3df5400dbdb75af4e643a4c553de;p=libreriscv.git --- diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index 8969ce6b4..4edd00d58 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -40,9 +40,11 @@ ALU. Multiply is tricky: 64 bit operands actually produce a 128-bit result. Most Scalar RISC ISAs have separate `mul-low-half` and `mul-hi-half` instructions, whilst some (OpenRISC) have "Accumulators" from which -the results of the multiply must be explicitly extracted. RISC advocates +the results of the multiply must be explicitly extracted. High +performance RISC advocates recommend "macro-op fusion" which is in effect where the second instruction -gains access to the cached copy of the HI result, which had already been +gains access to the cached copy of the HI half of the +multiply redult, which had already been computed by the first. This approach quickly complicates the internal microarchitecture, especially at the decode phase.