From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 13 Mar 2020 22:36:19 +0000 (+0000)
Subject: allow over-ride of address match function in PartialAddrMatch
X-Git-Tag: div_pipeline~1703
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8456d3797ab11613c76b73eec3fdce603e164628;p=soc.git

allow over-ride of address match function in PartialAddrMatch
---

diff --git a/src/soc/scoreboard/addr_match.py b/src/soc/scoreboard/addr_match.py
index e42bbe52..e03b036f 100644
--- a/src/soc/scoreboard/addr_match.py
+++ b/src/soc/scoreboard/addr_match.py
@@ -60,9 +60,10 @@ class PartialAddrMatch(Elaboratable):
         comb = m.d.comb
         sync = m.d.sync
 
+        # array of address-latches
         m.submodules.l = l = SRLatch(llen=self.n_adr, sync=False)
-        addrs_r = Array(Signal(self.bitwid, name="a_r") \
-                                for i in range(self.n_adr))
+        self.addrs_r = addrs_r = Array(Signal(self.bitwid, name="a_r") \
+                                       for i in range(self.n_adr))
 
         # latch set/reset
         comb += l.s.eq(self.addr_en_i)
@@ -77,16 +78,18 @@ class PartialAddrMatch(Elaboratable):
         for i in range(self.n_adr):
             match = []
             for j in range(self.n_adr):
-                if i == j:
-                    match.append(Const(0)) # don't match against self!
-                else:
-                    match.append(addrs_r[i] == addrs_r[j])
+                match.append(self.is_match(i, j))
             comb += self.addr_nomatch_a_o[i].eq(~Cat(*match) & l.q)
             matchgrp.append(self.addr_nomatch_a_o[i] == l.q)
         comb += self.addr_nomatch_o.eq(Cat(*matchgrp) & l.q)
             
         return m
 
+    def is_match(self, i, j):
+        if i == j:
+            return Const(0) # don't match against self!
+        return self.addrs_r[i] == self.addrs_r[j]
+
     def __iter__(self):
         yield from self.addrs_i
         yield self.addr_we_i
@@ -98,6 +101,12 @@ class PartialAddrMatch(Elaboratable):
         return list(self)
 
 
+class PartialAddrBitmap(PartialAddrMatch):
+    def __init__(self, n_adr, bitwid, bit_len):
+        PartialAddrMatch.__init__(self, n_adr, bitwid)
+        self.bitlen = bitlen # number of bits to turn into unary
+
+
 def part_addr_sim(dut):
     yield dut.dest_i.eq(1)
     yield dut.issue_i.eq(1)