From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 21:51:37 +0000 (-0700)
Subject: Missing newline
X-Git-Tag: working-ls180~1208^2~307
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8469d9fe9ff0a819c6b67aa6121cfd01cd1d0665;p=yosys.git

Missing newline
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f65ae87f5..b6b22284c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -139,7 +139,7 @@ struct SynthXilinxPass : public Pass
 		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
 		log("        clean\n");
 		log("        shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
-		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
+		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v\n");
 		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
 		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
 		log("\n");