From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Oct 2018 05:51:46 +0000 (+0100)
Subject: add in predication for immediate, for C.LWSP
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=846b8068a346a44f226ab4629ddb2a27b85964b3;p=riscv-isa-sim.git

add in predication for immediate, for C.LWSP
---

diff --git a/id_regs.py b/id_regs.py
index cd82b60..782cbcb 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -62,11 +62,12 @@ drlookup = { 'rd': 0, 'frd': 0, 'rs1': 1, 'rs2': 2, 'rs3': 3,
              'rvc_frs2': 2, 'rvc_frs2s': 2,
              }
 
-def find_registers(fname, twin_predication):
+def find_registers(fname, insn, twin_predication, immed_offset):
     # HACK! macro-skipping of instructions too painful
     for notparallel in ['csr', 'lui', 'c_j', 'wfi', 'auipc',
                         'dret', 'uret', 'mret', 'sret',
-                        'lr_d', 'lr_w', 'sc_d', 'sc_w']:
+                        'lr_d', 'lr_w', 'sc_d', 'sc_w',
+                        'c_addi4spn', 'c_addi16sp']:
         if notparallel in fname:
             return skip
     res = []
@@ -125,6 +126,11 @@ def find_registers(fname, twin_predication):
     res.append('#define REGS_PATTERN 0x%x' % isintfloat)
 
     predargs = ['dest_pred'] * 4
+    if immed_offset: # C.LWSP
+        predargs.append('&src_pred')
+        fsrc = insn in ['c_flwsp', 'c_fldsp']
+        res.append('#define SRC_PREDINT %d' % (0 if fsrc else 1))
+
     if twin_predication:
         found = None
         for search in ['rs1', 'rs2', 'rs3', 'rvc_rs1', 'rvc_rs1s',
@@ -140,10 +146,13 @@ def find_registers(fname, twin_predication):
             res.append('#define SRC_PREDINT %d' % (0 if fsrc else 1))
             res.append('#define SRC_REG %s' % found)
 
+    if len(predargs) == 4:
+        predargs.append('NULL')
+
     res.append('#define PRED_ARGS %s' % ','.join(predargs))
     offsargs = []
-    for i in range(4):
-        offsargs.append(predargs[i].replace('pred', 'offs'))
+    for i in range(len(predargs)):
+        offsargs.append(predargs[i].replace('pred', 'offs').replace("&", ''))
     res.append('#define OFFS_ARGS %s' % ','.join(offsargs))
 
     return '\n'.join(res)
@@ -154,6 +163,7 @@ if __name__ == '__main__':
         regsname = "regs_%s.h" % insn
         regsname = os.path.join(insns_dir, regsname)
         twin_predication = False
+        immed_offset = False
         with open(regsname, "w") as f:
             txt = "\n#define INSN_%s\n" % insn.upper()
             # help identify type of register
@@ -163,8 +173,11 @@ if __name__ == '__main__':
                 twin_predication = True
                 txt += "#define INSN_TYPE_LOAD\n"
             elif insn in ['c_lwsp', 'c_ldsp', 'c_lqsp', 'c_flwsp', 'c_fldsp']:
+                twin_predication = True
+                immed_offset = True
                 txt += "\n#define INSN_TYPE_C_STACK_LD\n"
             elif insn in ['c_swsp', 'c_sdsp', 'c_sqsp', 'c_fswsp', 'c_fsdsp']:
+                twin_predication = True
                 txt += "\n#define INSN_TYPE_C_STACK_ST\n"
             elif insn in ['c_lw', 'c_ld', 'c_lq', 'c_flw', 'c_fld']:
                 txt += "\n#define INSN_TYPE_C_LD\n"
@@ -188,5 +201,5 @@ if __name__ == '__main__':
                 txt += "#define INSN_TYPE_FP_BRANCH\n"
             if twin_predication:
                 txt += "\n#define INSN_CATEGORY_TWINPREDICATION\n"
-            txt += find_registers(fname, twin_predication)
+            txt += find_registers(fname, insn, twin_predication, immed_offset)
             f.write(txt)
diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 83b04d8..7eaa7d2 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -33,8 +33,12 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
             xstr(INSN), INSNCODE, s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
             vlen);
 #ifdef INSN_CATEGORY_TWINPREDICATION
+#ifdef INSN_TYPE_C_STACK_LD
+    src_pred = insn.predicate(X_SP, SRC_PREDINT, zeroingsrc);
+#else
     src_pred = insn.predicate(s_insn.SRC_REG(), SRC_PREDINT, zeroingsrc);
 #endif
+#endif
 #ifdef DEST_PREDINT
   // use the ORIGINAL, i.e. NON-REDIRECTED, register here
     dest_pred = insn.predicate(s_insn.DEST_REG(), DEST_PREDINT, zeroing);
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 45c0ae5..8065013 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -22,7 +22,8 @@ class sv_insn_t: public insn_t
 public:
   sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f,
             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
-            int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3) :
+            uint64_t *p_im,
+            int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_imm) :
             insn_t(bits), p(pr), vloop_continue(false), fimap(f),
             offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
             prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3) {}