From: H.J. Lu <hongjiu.lu@intel.com>
Date: Wed, 15 May 2019 15:22:08 +0000 (+0000)
Subject: i386: Make _mm_empty () as NOP without MMX
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84791fca67654942f39586b56166fcf22ef77553;p=gcc.git

i386: Make _mm_empty () as NOP without MMX

With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
without MMX.

	PR target/89021
	* config/i386/mmx.md (mmx_<emms>): Renamed to ...
	(*mmx_<emms>): This.
	(mmx_<emms>): New expander.

From-SVN: r271240
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2170b2f2188..9022014b3e7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/89021
+	* config/i386/mmx.md (mmx_<emms>): Renamed to ...
+	(*mmx_<emms>): This.
+	(mmx_<emms>): New expander.
+
 2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/89021
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 6504ebb17ef..8ffe4f7dfdb 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1874,7 +1874,35 @@
   [(UNSPECV_EMMS "emms")
    (UNSPECV_FEMMS "femms")])
 
-(define_insn "mmx_<emms>"
+(define_expand "mmx_<emms>"
+  [(parallel
+    [(unspec_volatile [(const_int 0)] EMMS)
+      (clobber (reg:XF ST0_REG))
+      (clobber (reg:XF ST1_REG))
+      (clobber (reg:XF ST2_REG))
+      (clobber (reg:XF ST3_REG))
+      (clobber (reg:XF ST4_REG))
+      (clobber (reg:XF ST5_REG))
+      (clobber (reg:XF ST6_REG))
+      (clobber (reg:XF ST7_REG))
+      (clobber (reg:DI MM0_REG))
+      (clobber (reg:DI MM1_REG))
+      (clobber (reg:DI MM2_REG))
+      (clobber (reg:DI MM3_REG))
+      (clobber (reg:DI MM4_REG))
+      (clobber (reg:DI MM5_REG))
+      (clobber (reg:DI MM6_REG))
+      (clobber (reg:DI MM7_REG))])]
+  "TARGET_MMX || TARGET_MMX_WITH_SSE"
+{
+   if (!TARGET_MMX)
+     {
+       emit_insn (gen_nop ());
+       DONE;
+     }
+})
+
+(define_insn "*mmx_<emms>"
   [(unspec_volatile [(const_int 0)] EMMS)
    (clobber (reg:XF ST0_REG))
    (clobber (reg:XF ST1_REG))