From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 21:23:39 +0000 (-0700)
Subject: Workaround issues exposed by gcc-4.8
X-Git-Tag: working-ls180~1208^2~114^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=848b023ccccc0cffa70d1aea45e558bdabb207b9;p=yosys.git

Workaround issues exposed by gcc-4.8
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index d50a38b7a..5f236992d 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -114,13 +114,20 @@ struct ConstEvalAig
 
 		RTLIL::Cell *cell = sig2driver.at(output);
 		RTLIL::SigBit sig_a = cell->getPort("\\A");
+		sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
+											   // that may occur does so here, and
+											   // not mid insertion (below)
 		sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end());
 		if (!inputs.count(sig_a))
 			compute_deps(sig_a, inputs);
 
 		if (cell->type == "$_AND_") {
 			RTLIL::SigSpec sig_b = cell->getPort("\\B");
+			sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
+												   // that may occur does so here, and
+												   // not mid insertion (below)
 			sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end());
+
 			if (!inputs.count(sig_b))
 				compute_deps(sig_b, inputs);
 		}