From: Luke Kenneth Casson Leighton Date: Thu, 28 Jul 2022 03:53:03 +0000 (+0100) Subject: clarify X-Git-Tag: opf_rfc_ls005_v1~986 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=849e57d731c5f92f35ecef6c4dd726cc47078fe6;p=libreriscv.git clarify --- diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index ac595322c..0d90d3787 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -34,7 +34,7 @@ * (19): RISC-V Vectors are not stand-alone, i.e. like SVE2 and AVX-512 are critically dependent on the Scalar ISA (an additional ~96 instructions for the Scalar RV64GC set (RV64GC is equivalent to the Linux Compliancy Level) * (20): Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction). However, like SVE2, the Maximum Vector length is a Silicon-partner choice, which creates similar limitations that SVP64 does not have. The RISC-V Founders strongly discouraged efforts by programmers to find out the Maximum Vector Length, as an effort to steer programmers towards Silicon-independent assembler. This requires all algorithms to contain a loop construct. - MAXVL in SVP64 is a Spec-hard-fixed quantity and consequently such loop constructs are not 100% necessary. + MAXVL in SVP64 is a Spec-hard-fixed quantity therefore loop constructs are not necessary 100% of the time. * (21): like SVP64 it is up to the hardware implementor to choose whether to support 128-bit elements. * (22): [NEC SX Aurora](https://ftp.libre-soc.org/NEC_SX_Aurora_TSUBASA_VectorEngine-as-manual-v1.2.pdf) is based on the original Cray Vectors * (23): [Aurora ISA guide](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf) Appendix-3 11.1 p508