From: Andrey Miroshnikov <andrey@technepisteme.xyz>
Date: Fri, 22 Jul 2022 18:09:11 +0000 (+0100)
Subject: removed question mark
X-Git-Tag: opf_rfc_ls005_v1~1125
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84a6e1769216db4f74c081890d224bb0d94fa370;p=libreriscv.git

removed question mark
---

diff --git a/openpower/svp64-primer/summary.tex b/openpower/svp64-primer/summary.tex
index 318125d8b..9523bfdf3 100644
--- a/openpower/svp64-primer/summary.tex
+++ b/openpower/svp64-primer/summary.tex
@@ -161,7 +161,7 @@ how a Vector's elements are sequentially and linearly mapped onto the
 
 \subsection{Simple Vectorisation}
 \acs{SV} is a Scalable Vector ISA designed for hybrid workloads (CPU, GPU,
-VPU, 3D?).  Includes features normally found only on Cray-style Supercomputers
+VPU, 3D).  Includes features normally found only on Cray-style Supercomputers
 (Cray-1, NEC SX-Aurora) and GPUs.  Keeps to a strict uniform RISC paradigm,
 leveraging a scalar ISA by using "Prefixing".
 \textbf{No dedicated vector opcodes exist in SV, at all}.