From: Luke Kenneth Casson Leighton Date: Fri, 26 Nov 2021 15:19:19 +0000 (+0000) Subject: early use of Array unnecessarily (all uses are static references X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84adeb12ecbb67a66099f788823609505cc9668d;p=soc.git early use of Array unnecessarily (all uses are static references not dynamic indexing: no pmux created or needed) --- diff --git a/src/soc/experiment/score6600_multi.py b/src/soc/experiment/score6600_multi.py index bd05747d..4c9b5505 100644 --- a/src/soc/experiment/score6600_multi.py +++ b/src/soc/experiment/score6600_multi.py @@ -364,15 +364,15 @@ class FunctionUnits(Elaboratable): wpnd.append(Signal(nf, name="wr_dst%d_pend_o" % j, reset_less=True)) - self.dest_i = Array(dst) # Dest in (top) - self.src_i = Array(src) # oper in (top) + self.dest_i = dst # Dest in (top) + self.src_i = src # oper in (top) # for Register File Select Lines (horizontal), per-reg - self.dst_rsel_o = Array(dsel) # dest reg (bot) - self.src_rsel_o = Array(rsel) # src reg (bot) + self.dst_rsel_o = dsel # dest reg (bot) + self.src_rsel_o = rsel # src reg (bot) - self.go_rd_i = Array(rd) - self.go_wr_i = Array(wr) + self.go_rd_i = rd + self.go_wr_i = wr self.go_die_i = Signal(n_int_alus, reset_less=True) self.fn_issue_i = Signal(n_int_alus, reset_less=True) diff --git a/src/soc/scoreboard/addr_match.py b/src/soc/scoreboard/addr_match.py index eee28398..66adafa4 100644 --- a/src/soc/scoreboard/addr_match.py +++ b/src/soc/scoreboard/addr_match.py @@ -33,7 +33,7 @@ Notes: from nmigen.compat.sim import run_simulation, Settle from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Const, Array, Cat, Elaboratable, Repl +from nmigen import Module, Signal, Const, Cat, Elaboratable, Repl from nmigen.lib.coding import Decoder from nmigen.utils import log2_int @@ -48,14 +48,14 @@ class PartialAddrMatch(Elaboratable): self.n_adr = n_adr self.bitwid = bitwid # inputs - self.addrs_i = Array(Signal(bitwid, name="addr") for i in range(n_adr)) + self.addrs_i = tuple(Signal(bitwid, name="addr") for i in range(n_adr)) # self.addr_we_i = Signal(n_adr, reset_less=True) # write-enable self.addr_en_i = Signal(n_adr, reset_less=True) # address latched in self.addr_rs_i = Signal(n_adr, reset_less=True) # address deactivated # output: a nomatch for each address plus individual nomatch signals self.addr_nomatch_o = Signal(n_adr, name="nomatch_o", reset_less=True) - self.addr_nomatch_a_o = Array(Signal(n_adr, reset_less=True, + self.addr_nomatch_a_o = tuple(Signal(n_adr, reset_less=True, name="nomatch_array_o") for i in range(n_adr)) @@ -69,7 +69,7 @@ class PartialAddrMatch(Elaboratable): # array of address-latches m.submodules.l = self.l = l = SRLatch(llen=self.n_adr, sync=False) - self.adrs_r = adrs_r = Array(Signal(self.bitwid, reset_less=True, + self.adrs_r = adrs_r = tuple(Signal(self.bitwid, reset_less=True, name="a_r") for i in range(self.n_adr)) @@ -183,14 +183,14 @@ class TwinPartialAddrBitmap(PartialAddrMatch): # input: length of the LOAD/STORE expwid = 1+self.lsbwid # XXX assume LD/ST no greater than 8 - self.lexp_i = Array(Signal(1 << expwid, reset_less=True, + self.lexp_i = tuple(Signal(1 << expwid, reset_less=True, name="len") for i in range(n_adr)) # input: full address - self.faddrs_i = Array(Signal(bitlen, reset_less=True, + self.faddrs_i = tuple(Signal(bitlen, reset_less=True, name="fadr") for i in range(n_adr)) # registers for expanded len - self.len_r = Array(Signal(expwid, reset_less=True, name="l_r") + self.len_r = tuple(Signal(expwid, reset_less=True, name="l_r") for i in range(self.n_adr)) def elaborate(self, platform): @@ -268,20 +268,20 @@ class PartialAddrBitmap(PartialAddrMatch): PartialAddrMatch.__init__(self, n_adr, self.midlen) # input: length of the LOAD/STORE - self.len_i = Array(Signal(lsbwid, reset_less=True, + self.len_i = tuple(Signal(lsbwid, reset_less=True, name="len") for i in range(n_adr)) # input: full address - self.faddrs_i = Array(Signal(bitlen, reset_less=True, + self.faddrs_i = tuple(Signal(bitlen, reset_less=True, name="fadr") for i in range(n_adr)) # intermediary: address + 1 - self.addr1s = Array(Signal(self.midlen, reset_less=True, + self.addr1s = tuple(Signal(self.midlen, reset_less=True, name="adr1") for i in range(n_adr)) # expanded lengths, needed in match expwid = 1+self.lsbwid # XXX assume LD/ST no greater than 8 - self.lexp = Array(Signal(1 << expwid, reset_less=True, + self.lexp = tuple(Signal(1 << expwid, reset_less=True, name="a_l") for i in range(self.n_adr)) @@ -291,7 +291,7 @@ class PartialAddrBitmap(PartialAddrMatch): # intermediaries adrs_r, l = self.adrs_r, self.l - len_r = Array(Signal(self.lsbwid, reset_less=True, + len_r = tuple(Signal(self.lsbwid, reset_less=True, name="l_r") for i in range(self.n_adr)) diff --git a/src/soc/scoreboard/addr_split.py b/src/soc/scoreboard/addr_split.py index c015599d..dd050b3b 100644 --- a/src/soc/scoreboard/addr_split.py +++ b/src/soc/scoreboard/addr_split.py @@ -8,7 +8,7 @@ Links: #from soc.experiment.pimem import PortInterface -from nmigen import Elaboratable, Module, Signal, Record, Array, Const, Cat +from nmigen import Elaboratable, Module, Signal, Record, Const, Cat from nmutil.latch import SRLatch, latchregister from nmigen.back.pysim import Simulator, Delay from nmigen.cli import verilog, rtlil @@ -97,12 +97,12 @@ class LDSTSplitter(Elaboratable): self.sld_o_valid = Signal(2, reset_less=True) self.sld_i_valid = Signal(2, reset_less=True) - self.sld_data_i = Array((LDData(cline_wid, "ld_data_i1"), + self.sld_data_i = tuple((LDData(cline_wid, "ld_data_i1"), LDData(cline_wid, "ld_data_i2"))) self.sst_o_valid = Signal(2, reset_less=True) self.sst_i_valid = Signal(2, reset_less=True) - self.sst_data_o = Array((LDData(cline_wid, "st_data_i1"), + self.sst_data_o = tuple((LDData(cline_wid, "st_data_i1"), LDData(cline_wid, "st_data_i2"))) def elaborate(self, platform): diff --git a/src/soc/scoreboard/dependence_cell.py b/src/soc/scoreboard/dependence_cell.py index c6cf4259..c3db10e4 100644 --- a/src/soc/scoreboard/dependence_cell.py +++ b/src/soc/scoreboard/dependence_cell.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Array, Cat, Repl +from nmigen import Module, Signal, Elaboratable, Cat, Repl from nmutil.latch import SRLatch from functools import reduce from operator import or_ @@ -43,7 +43,7 @@ class DependencyRow(Elaboratable): # inputs self.dest_i = Signal(n_reg, reset_less=True) # Dest in (top) - self.src_i = Array(src) # operands in (top) + self.src_i = tuple(src) # operands in (top) self.issue_i = Signal(reset_less=True) # Issue in (top) self.rd_pend_i = Signal(n_reg, reset_less=True) # Read pend in (top) @@ -60,11 +60,11 @@ class DependencyRow(Elaboratable): # for Register File Select Lines (vertical) self.dest_rsel_o = Signal(n_reg, reset_less=True) # dest reg sel (bot) - self.src_rsel_o = Array(rsel) # src reg sel (bot) + self.src_rsel_o = tuple(rsel) # src reg sel (bot) # for Function Unit "forward progress" (horizontal) self.dest_fwd_o = Signal(n_reg, reset_less=True) # dest FU fw (right) - self.src_fwd_o = Array(fwd) # src FU fw (right) + self.src_fwd_o = tuple(fwd) # src FU fw (right) def elaborate(self, platform): m = Module() diff --git a/src/soc/scoreboard/fn_unit.py b/src/soc/scoreboard/fn_unit.py index d0e7004c..e6d4c341 100644 --- a/src/soc/scoreboard/fn_unit.py +++ b/src/soc/scoreboard/fn_unit.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Cat, Array, Const, Elaboratable +from nmigen import Module, Signal, Cat, Const, Elaboratable from nmigen.lib.coding import Decoder from nmutil.latch import SRLatch, latchregister @@ -46,7 +46,7 @@ class FnUnit(Elaboratable): if n_dests > 1: self.rfile_sel_i = Signal(range(n_dests), reset_less=True) else: - self.rfile_sel_i = Const(0) # no selection. gets Array[0] + self.rfile_sel_i = Const(0) # no selection. gets 0 self.dest_i = Signal(range(wid), reset_less=True) # Dest R# in (top) self.src1_i = Signal(range(wid), reset_less=True) # oper1 R# in (top) self.src2_i = Signal(range(wid), reset_less=True) # oper2 R# in (top) @@ -56,7 +56,7 @@ class FnUnit(Elaboratable): self.go_rd_i = Signal(reset_less=True) # Go Read in (left) self.req_rel_i = Signal(reset_less=True) # request release (left) - self.g_xx_pend_i = Array(Signal(wid, reset_less=True, name="g_pend_i") + self.g_xx_pend_i = tuple(Signal(wid, reset_less=True, name="g_pend_i") for i in range(n_dests)) # global rd (right) self.g_wr_pend_i = Signal(wid, reset_less=True) # global wr (right) @@ -68,14 +68,14 @@ class FnUnit(Elaboratable): # outputs self.readable_o = Signal(reset_less=True) # Readable out (right) - self.writable_o = Array(Signal(reset_less=True, name="writable_o") + self.writable_o = tuple(Signal(reset_less=True, name="writable_o") for i in range(n_dests)) # writable out (right) self.busy_o = Signal(reset_less=True) # busy out (left) self.src1_pend_o = Signal(wid, reset_less=True) # src1 pending self.src2_pend_o = Signal(wid, reset_less=True) # src1 pending self.rd_pend_o = Signal(wid, reset_less=True) # rd pending (right) - self.xx_pend_o = Array(Signal(wid, reset_less=True, name="pend_o") + self.xx_pend_o = tuple(Signal(wid, reset_less=True, name="pend_o") for i in range(n_dests)) # wr pending (right) def elaborate(self, platform): diff --git a/src/soc/scoreboard/fu_fu_matrix.py b/src/soc/scoreboard/fu_fu_matrix.py index cc2c1b96..35e015d7 100644 --- a/src/soc/scoreboard/fu_fu_matrix.py +++ b/src/soc/scoreboard/fu_fu_matrix.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Array, Cat, Const +from nmigen import Module, Signal, Elaboratable, Cat, Const from .fu_dep_cell import FUDependenceCell from .fu_picker_vec import FU_Pick_Vec @@ -36,7 +36,7 @@ class FUFUDepMatrix(Elaboratable): # --- # matrix of dependency cells # --- - dm = Array(FUDependenceCell(f, self.n_fu_col) \ + dm = tuple(FUDependenceCell(f, self.n_fu_col) \ for f in range(self.n_fu_row)) for y in range(self.n_fu_row): setattr(m.submodules, "dm%d" % y, dm[y]) @@ -44,7 +44,7 @@ class FUFUDepMatrix(Elaboratable): # --- # array of Function Unit Readable/Writable: row-length, horizontal # --- - fur = Array(FU_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col)) + fur = tuple(FU_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col)) for x in range(self.n_fu_col): setattr(m.submodules, "fur_x%d" % (x), fur[x]) diff --git a/src/soc/scoreboard/fu_mem_matrix.py b/src/soc/scoreboard/fu_mem_matrix.py index 47d6bcc2..08bdc78e 100644 --- a/src/soc/scoreboard/fu_mem_matrix.py +++ b/src/soc/scoreboard/fu_mem_matrix.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Array, Cat, Const +from nmigen import Module, Signal, Elaboratable, Cat, Const from soc.scoreboard.fumem_dep_cell import FUMemDependenceCell from soc.scoreboard.fu_mem_picker_vec import FUMem_Pick_Vec @@ -36,7 +36,7 @@ class FUMemDepMatrix(Elaboratable): # --- # matrix of dependency cells # --- - dm = Array(FUMemDependenceCell(f, self.n_fu_col) \ + dm = tuple(FUMemDependenceCell(f, self.n_fu_col) \ for f in range(self.n_fu_row)) for y in range(self.n_fu_row): setattr(m.submodules, "dm%d" % y, dm[y]) @@ -44,7 +44,7 @@ class FUMemDepMatrix(Elaboratable): # --- # array of Function Unit Readable/Writable: row-length, horizontal # --- - fur = Array(FUMem_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col)) + fur = tuple(FUMem_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col)) for x in range(self.n_fu_col): setattr(m.submodules, "fur_x%d" % (x), fur[x]) diff --git a/src/soc/scoreboard/fu_reg_matrix.py b/src/soc/scoreboard/fu_reg_matrix.py index 06380434..35fcac0d 100644 --- a/src/soc/scoreboard/fu_reg_matrix.py +++ b/src/soc/scoreboard/fu_reg_matrix.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Array, Cat, Repl +from nmigen import Module, Signal, Elaboratable, Cat, Repl from soc.scoreboard.dependence_cell import DependencyRow from soc.scoreboard.fu_wr_pending import FU_RW_Pend @@ -46,7 +46,7 @@ class FURegDepMatrix(Elaboratable): pend.append(Signal(nf, name="rd_src%d_pend_o" % j, reset_less=True)) self.dest_i = Signal(n_reg_col, reset_less=True) # Dest in (top) - self.src_i = Array(src) # oper in (top) + self.src_i = tuple(src) # oper in (top) # cancellation array (from Address Matching), ties in with go_die_i self.cancel = cancel @@ -64,12 +64,12 @@ class FURegDepMatrix(Elaboratable): # for Register File Select Lines (horizontal), per-reg self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot) - self.src_rsel_o = Array(rsel) # src reg (bot) + self.src_rsel_o = tuple(rsel) # src reg (bot) # for Function Unit "forward progress" (vertical), per-FU self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right) self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right) - self.rd_src_pend_o = Array(pend) # src1 pending + self.rd_src_pend_o = tuple(pend) # src1 pending def elaborate(self, platform): m = Module() @@ -81,7 +81,7 @@ class FURegDepMatrix(Elaboratable): # matrix of dependency cells # --- cancel_mode = self.cancel is not None - dm = Array(DependencyRow(self.n_reg_col, self.n_src, cancel_mode) \ + dm = tuple(DependencyRow(self.n_reg_col, self.n_src, cancel_mode) \ for r in range(self.n_fu_row)) for fu in range(self.n_fu_row): setattr(m.submodules, "dr_fu%d" % fu, dm[fu]) @@ -89,7 +89,7 @@ class FURegDepMatrix(Elaboratable): # --- # array of Function Unit Pending vectors # --- - fupend = Array(FU_RW_Pend(self.n_reg_col, self.n_src) \ + fupend = tuple(FU_RW_Pend(self.n_reg_col, self.n_src) \ for f in range(self.n_fu_row)) for fu in range(self.n_fu_row): setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu]) @@ -97,7 +97,7 @@ class FURegDepMatrix(Elaboratable): # --- # array of Register Reservation vectors # --- - regrsv = Array(Reg_Rsv(self.n_fu_row, self.n_src) \ + regrsv = tuple(Reg_Rsv(self.n_fu_row, self.n_src) \ for r in range(self.n_reg_col)) for rn in range(self.n_reg_col): setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn]) diff --git a/src/soc/scoreboard/fu_wr_pending.py b/src/soc/scoreboard/fu_wr_pending.py index d0bcb954..ea464dce 100644 --- a/src/soc/scoreboard/fu_wr_pending.py +++ b/src/soc/scoreboard/fu_wr_pending.py @@ -1,4 +1,4 @@ -from nmigen import Elaboratable, Module, Signal, Array +from nmigen import Elaboratable, Module, Signal class FU_RW_Pend(Elaboratable): @@ -13,7 +13,7 @@ class FU_RW_Pend(Elaboratable): for i in range(n_src): j = i + 1 # name numbering to match src1/src2 src.append(Signal(reg_count, name="src%d" % j, reset_less=True)) - self.src_fwd_i = Array(src) + self.src_fwd_i = tuple(src) self.reg_wr_pend_o = Signal(reset_less=True) self.reg_rd_pend_o = Signal(reset_less=True) diff --git a/src/soc/scoreboard/group_picker.py b/src/soc/scoreboard/group_picker.py index af1bb765..45ff1b41 100644 --- a/src/soc/scoreboard/group_picker.py +++ b/src/soc/scoreboard/group_picker.py @@ -45,7 +45,7 @@ In theory (and in practice!) the following is possible: from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Array +from nmigen import Module, Signal, Elaboratable #from nmutil.picker import MultiPriorityPicker as MPP from nmutil.picker import PriorityPicker @@ -75,14 +75,14 @@ class GroupPicker(Elaboratable): wi.append(Signal(wid, name="writable%d_i" % i, reset_less=True)) # inputs - self.rd_rel_i = Array(rdr) # go read in (top) - self.req_rel_i = Array(wrr) # release request in (top) - self.readable_i = Array(ri) # readable in (top) - self.writable_i = Array(wi) # writable in (top) + self.rd_rel_i = tuple(rdr) # go read in (top) + self.req_rel_i = tuple(wrr) # release request in (top) + self.readable_i = tuple(ri) # readable in (top) + self.writable_i = tuple(wi) # writable in (top) # outputs - self.go_rd_o = Array(rd) # go read (bottom) - self.go_wr_o = Array(wr) # go write (bottom) + self.go_rd_o = tuple(rd) # go read (bottom) + self.go_wr_o = tuple(wr) # go write (bottom) def elaborate(self, platform): m = Module() diff --git a/src/soc/scoreboard/ldst_matrix.py b/src/soc/scoreboard/ldst_matrix.py index e8911241..79b82249 100644 --- a/src/soc/scoreboard/ldst_matrix.py +++ b/src/soc/scoreboard/ldst_matrix.py @@ -32,7 +32,7 @@ Notes: from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Array, Cat, Const +from nmigen import Module, Signal, Elaboratable, Cat, Const from .ldst_dep_cell import LDSTDepCell @@ -69,7 +69,7 @@ class LDSTDepMatrix(Elaboratable): # --- # matrix of dependency cells. actually, LDSTDepCell is a row, now # --- - dm = Array(LDSTDepCell(self.n_ldst) for f in range(self.n_ldst)) + dm = tuple(LDSTDepCell(self.n_ldst) for f in range(self.n_ldst)) for fu in range(self.n_ldst): setattr(m.submodules, "dm_fu%d" % (fu), dm[fu]) diff --git a/src/soc/scoreboard/mem_dependence_cell.py b/src/soc/scoreboard/mem_dependence_cell.py index 2958d864..382400b7 100644 --- a/src/soc/scoreboard/mem_dependence_cell.py +++ b/src/soc/scoreboard/mem_dependence_cell.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Array, Cat, Repl +from nmigen import Module, Signal, Elaboratable, Cat, Repl from nmutil.latch import SRLatch diff --git a/src/soc/scoreboard/mem_fu_matrix.py b/src/soc/scoreboard/mem_fu_matrix.py index 6b9ce140..53c74010 100644 --- a/src/soc/scoreboard/mem_fu_matrix.py +++ b/src/soc/scoreboard/mem_fu_matrix.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Elaboratable, Array, Cat +from nmigen import Module, Signal, Elaboratable, Cat from soc.scoreboard.mem_dependence_cell import MemDepRow from soc.scoreboard.mem_fu_pending import MemFU_Pend @@ -45,21 +45,21 @@ class MemFUDepMatrix(Elaboratable): # --- # matrix of dependency cells # --- - dm = Array(MemDepRow(self.n_reg_col) for r in range(self.n_fu_row)) + dm = tuple(MemDepRow(self.n_reg_col) for r in range(self.n_fu_row)) for fu in range(self.n_fu_row): setattr(m.submodules, "dr_fu%d" % fu, dm[fu]) # --- # array of Function Unit Pending vectors # --- - fupend = Array(MemFU_Pend(self.n_reg_col) for f in range(self.n_fu_row)) + fupend = tuple(MemFU_Pend(self.n_reg_col) for f in range(self.n_fu_row)) for fu in range(self.n_fu_row): setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu]) # --- # array of Register Reservation vectors # --- - regrsv = Array(Mem_Rsv(self.n_fu_row) for r in range(self.n_reg_col)) + regrsv = tuple(Mem_Rsv(self.n_fu_row) for r in range(self.n_reg_col)) for rn in range(self.n_reg_col): setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn]) diff --git a/src/soc/scoreboard/memfu.py b/src/soc/scoreboard/memfu.py index 553ebb5e..fd0902ad 100644 --- a/src/soc/scoreboard/memfu.py +++ b/src/soc/scoreboard/memfu.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Array, Elaboratable +from nmigen import Module, Signal, Elaboratable from soc.scoreboard.fu_fu_matrix import FUFUDepMatrix from soc.scoreboard.mdm import FUMemMatchMatrix @@ -31,7 +31,7 @@ class MemFunctionUnits(Elaboratable): self.fn_issue_i = Signal(n_ldsts, reset_less=True) # address matching - self.addrs_i = Array(Signal(self.bitwid, name="addrs_i%d" % i) \ + self.addrs_i = tuple(Signal(self.bitwid, name="addrs_i%d" % i) \ for i in range(n_ldsts)) #self.addr_we_i = Signal(n_ldsts) # write-enable for incoming address self.addr_en_i = Signal(n_ldsts) # address latched in diff --git a/src/soc/scoreboard/reg_select.py b/src/soc/scoreboard/reg_select.py index 3919cce3..d6655323 100644 --- a/src/soc/scoreboard/reg_select.py +++ b/src/soc/scoreboard/reg_select.py @@ -1,4 +1,4 @@ -from nmigen import Elaboratable, Module, Signal, Array +from nmigen import Elaboratable, Module, Signal class Reg_Rsv(Elaboratable): @@ -9,7 +9,7 @@ class Reg_Rsv(Elaboratable): self.n_src = n_src self.fu_count = fu_count self.dest_rsel_i = Signal(fu_count, reset_less=True) - self.src_rsel_i = Array(Signal(fu_count, name="src_rsel_i", + self.src_rsel_i = tuple(Signal(fu_count, name="src_rsel_i", reset_less=True) \ for i in range(n_src)) self.dest_rsel_o = Signal(reset_less=True) diff --git a/src/soc/scoreboard/shadow.py b/src/soc/scoreboard/shadow.py index d99d37a8..36f92509 100644 --- a/src/soc/scoreboard/shadow.py +++ b/src/soc/scoreboard/shadow.py @@ -1,6 +1,6 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from nmigen import Module, Signal, Cat, Array, Const, Elaboratable, Repl +from nmigen import Module, Signal, Cat, Const, Elaboratable, Repl from nmigen.lib.coding import Decoder from soc.scoreboard.shadow_fn import ShadowFn @@ -42,11 +42,11 @@ class ShadowMatrix(Elaboratable): # inputs self.issue_i = Signal(n_fus, reset_less=True) self.reset_i = Signal(n_fus, reset_less=True) - self.shadow_i = Array(Signal(shadow_wid, name="sh_i", reset_less=True) \ + self.shadow_i = tuple(Signal(shadow_wid, name="sh_i", reset_less=True) \ for f in range(n_fus)) - self.s_fail_i = Array(Signal(shadow_wid, name="fl_i", reset_less=True) \ + self.s_fail_i = tuple(Signal(shadow_wid, name="fl_i", reset_less=True) \ for f in range(n_fus)) - self.s_good_i = Array(Signal(shadow_wid, name="gd_i", reset_less=True) \ + self.s_good_i = tuple(Signal(shadow_wid, name="gd_i", reset_less=True) \ for f in range(n_fus)) # outputs self.go_die_o = Signal(n_fus, reset_less=True) @@ -176,7 +176,7 @@ class WaWGrid(Elaboratable): self.shadow_i = Signal(shadow_wid, reset_less=True) self.fu_i = Signal(n_fus, reset_less=True) - self.waw_o = Array(Signal(shadow_wid, name="waw_o", reset_less=True) \ + self.waw_o = tuple(Signal(shadow_wid, name="waw_o", reset_less=True) \ for f in range(n_fus)) def elaborate(self, platform):