From: lkcl <lkcl@web>
Date: Mon, 3 Oct 2022 19:55:49 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~221
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84b70fc1efc6e1d16968bfa2a889879165576e45;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index 7f96112bf..ac7c8da87 100644
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -60,6 +60,13 @@ Notes:
 2. There is no need for Special Registers (FP Flags) because this
   is an immediate loading instruction.  No FPR Load Operations
   alter `FPSCR` and neither does `lxvkq`
+3. EXT001 Variants which also save similar Data-Load and Data-TLB
+  lookups are mentioned for completeness but not included as part
+  of this RFC. Another Stakeholder may wish to consider submitting
+  them.
+4. `fishmv` as a Read-Modify-Write saves five unnecessary bits, making
+  the difference between a VA/DX-Form and requiring an entire Major
+  Opcode.
 
 ----------------
 
@@ -100,3 +107,50 @@ fmvis f4, 0x7F80 # writes +Infinity to f4
 fmvis f4, 0xFF80 # writes -Infinity to f4
 fmvis f4, 0x3FFF # writes +1.9921875 to f4
 ```
+
+## Float Immediate Second-Half MV <a name="fishmv"></a>
+
+`fishmv FRS, D`
+
+DX-Form:
+
+|  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form    |
+|--------|------|-------|-------|-------|-----|---------|
+|  Major | FRS  | d1    | d0    | XO    | d2  | DX-Form |
+
+Pseudocode:
+
+    n <- (FRS)                     # read FRS
+    fp32 <- SINGLE(n)              # convert to FP32
+    fp32[16:31] <- d0 || d1 || d2  # replace LSB half
+    FRS <- DOUBLE(fp32)            # convert back to FP64
+
+Special registers altered:
+
+    None
+
+Strategically similar to how `oris` is used to construct
+32-bit Integers, an additional 16-bits of immediate is
+inserted into `FRS` to extend its accuracy to
+a full FP32 (stored as usual in FP64 Format within the FPR).
+If a prior `fmvis` instruction had been used to
+set the upper 16-bits from an FP32 value, `fishmv` contains the
+lower 16-bits.
+
+**This instruction performs a Read-Modify-Write.** *FRS is read, the
+additional
+16 bit immediate inserted, and the result also written to FRS.
+`fishmv` may be macro-op-fused with `fmvis`*
+
+Example:
+
+```
+# these two combined instructions write 0x3f808000
+# into f4 as an FP32 to be converted to an FP64.
+# actual contents in f4 after conversion: 0x3ff0_1000_0000_0000
+# first the upper bits, happens to be +1.0
+fmvis f4, 0x3F80 # writes +1.0 to f4
+# now write the lower 16 bits of an FP32
+fishmv f4, 0x8000 # writes +1.00390625 to f4
+```
+