From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Feb 2022 13:50:34 +0000 (+0000)
Subject: add external_core_top.v to build for ulx3s
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84c54a10f29f2b2f4b7246640b9aec68cb6cd94e;p=microwatt.git

add external_core_top.v to build for ulx3s
---

diff --git a/Makefile b/Makefile
index 88cbdbe..f4dc54d 100644
--- a/Makefile
+++ b/Makefile
@@ -222,6 +222,7 @@ else
                 core_dummy.vhdl
     fpga_files = $(_fpga_files) $(_soc_files)
     synth_files = $(util_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
+    soc_extra_v = external_core_top.v
 endif
 
 GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \