From: lkcl <lkcl@web>
Date: Mon, 20 Jun 2022 12:12:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84c726e240a912ec95ec3f26b7660bf0a5c47637;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index d22dfb5bc..ce947543f 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -13,7 +13,6 @@ Links:
 * [[simple_v_extension/specification/bitmanip]] previous version,
   contains pseudocode for sof, sif, sbf
 
-
 The core OpenPOWER ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. However, certain classes of instructions only make sense in a Vector context: AVX512 conflictd for example.  This section includes such examples.  Many of them are from the RISC-V Vector ISA (with thanks to the efforts of RVV's contributors)
 
 Notes:
@@ -236,35 +235,11 @@ Example
                        vmsof.m v2, v3, v0.t
      0 1 x x x x 0 0   v2 content
 
-Pseudo-code:
-
-    def sof(rd, rs1, rs2):
-        rd = 0
-        setting_mode = rs2 == x0 or (regs[rs2] & 1)
-
-        while i < XLEN:
-            bit = 1<<i
-
-            # only reenable when predicate in use, and bit valid
-            if !setting_mode && rs2 != x0:
-                if (regs[rs2] & bit):
-                    # back into "setting" mode
-                    setting_mode = True
-
-            # skipping mode
-            if !setting_mode:
-                # skip any more 1s
-                if regs[rs1] & bit == 1:
-                    i += 1
-                    continue
-
-            # setting mode, search for 1
-            if regs[rs1] & bit: # found a bit in rs1:
-                regs[rd] |= bit # only set when search succeeds
-                setting_mode = False
-                # next loop starts skipping
+Executable demo:
 
-            i += 1
+```
+[[!inline quick="yes" raw="yes" pages="openpower/sv/sbf.py"]]
+```
 
 # Carry-lookahead