From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Tue, 11 Apr 2023 18:27:23 +0000 (+0300)
Subject: ppc/svp64: support avgadd instructions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84d4bd4af5a7db38d925a3b9e77d6704f77e3665;p=binutils-gdb.git

ppc/svp64: support avgadd instructions
---

diff --git a/gas/testsuite/gas/ppc/avgadd.d b/gas/testsuite/gas/ppc/avgadd.d
new file mode 100644
index 00000000000..062e78358e2
--- /dev/null
+++ b/gas/testsuite/gas/ppc/avgadd.d
@@ -0,0 +1,14 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:\s+(5b e0 06 9c|9c 06 e0 5b)\s+avgadd\s+r31,r0,r0
+.*:\s+(58 1f 06 9c|9c 06 1f 58)\s+avgadd\s+r0,r31,r0
+.*:\s+(58 00 fe 9c|9c fe 00 58)\s+avgadd\s+r0,r0,r31
+.*:\s+(5b e0 06 9d|9d 06 e0 5b)\s+avgadd.\s+r31,r0,r0
+.*:\s+(58 1f 06 9d|9d 06 1f 58)\s+avgadd.\s+r0,r31,r0
+.*:\s+(58 00 fe 9d|9d fe 00 58)\s+avgadd.\s+r0,r0,r31
diff --git a/gas/testsuite/gas/ppc/avgadd.s b/gas/testsuite/gas/ppc/avgadd.s
new file mode 100644
index 00000000000..92d24801930
--- /dev/null
+++ b/gas/testsuite/gas/ppc/avgadd.s
@@ -0,0 +1,6 @@
+avgadd 31,0,0
+avgadd 0,31,0
+avgadd 0,0,31
+avgadd. 31,0,0
+avgadd. 0,31,0
+avgadd. 0,0,31
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 286f1fe30cc..ab2cb234967 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -164,3 +164,4 @@ run_dump_test "svindex"
 run_dump_test "fmvis"
 run_dump_test "fishmv"
 run_dump_test "minmax"
+run_dump_test "avgadd"
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index f9a4cb3f68b..62aafe9e743 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -7041,6 +7041,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"maxs",	XRC(22,462,0),	X_MASK,	SVP64,	PPCVLE,	{RT, RA, RB}},
 {"maxs.",	XRC(22,462,1),	X_MASK,	SVP64,	PPCVLE,	{RT, RA, RB}},
 
+{"avgadd",	XRC(22,846,0),	X_MASK,	SVP64,	PPCVLE,	{RT, RA, RB}},
+{"avgadd.",	XRC(22,846,1),	X_MASK,	SVP64,	PPCVLE,	{RT, RA, RB}},
+
 {"rotlw",	MME(23,31,0),	MMBME_MASK,  PPCCOM,	PPCVLE|EXT,	{RA, RS, RB}},
 {"rlwnm",	M(23,0),	M_MASK,	     PPCCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},
 {"rlnm",	M(23,0),	M_MASK,	     PWRCOM,	PPCVLE,		{RA, RS, RB, MBE, ME}},