From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 Oct 2018 08:28:33 +0000 (+0100)
Subject: redirect DO_WRITE_FREG and READ_FREG and others
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84e8c5b9c1a88990e368709f9ca08b910336cac1;p=riscv-isa-sim.git

redirect DO_WRITE_FREG and READ_FREG and others

no longer adding the offset onto the register in sv_insn_t,
now to be done in sv_proc_t WRITE_REG/READ_REG, where the
element width can be examined (finally)
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 03ac631..cc61ade 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -227,7 +227,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%g\n",
                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs),
-                (double)(READ_FREG(insn._rd().reg)).v[0]);
+                (double)(READ_FREG(insn._rd())).v[0]);
 #endif
       }
       if (insn.stop_vloop())
diff --git a/riscv/sv.cc b/riscv/sv.cc
index 7a07d80..16bcba5 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -132,7 +132,7 @@ bool sv_insn_t::sv_check_reg(bool intreg, uint64_t reg)
  */
 reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int *voffs)
 {
-  reg_spec_t spec = {reg, voffs};
+  reg_spec_t spec = {reg, NULL};
   // okaay so first determine which map to use.  intreg is passed
   // in (ultimately) from id_regs.py's examination of the use of
   // FRS1/RS1, WRITE_FRD/WRITE_RD, which in turn gets passed
@@ -162,7 +162,7 @@ reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int *voffs)
   vloop_continue = true;
 
   // aaand now, as it's a "vector", FINALLY we can pass the loop-offset
-  spec.reg = reg + *voffs;
+  spec.reg = reg; //+ *voffs;
   spec.offset = voffs;
   return spec;
 }
@@ -218,10 +218,10 @@ reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing)
 reg_spec_t sv_insn_t::predicated(reg_spec_t const& spec, uint64_t pred)
 {
     reg_spec_t res = spec;
-    //if (spec.offset == NULL)
-    //{
-    //    return res;
-    //}
+    if (spec.offset == NULL)
+    {
+        return res;
+    }
     if (pred & (1<<(*spec.offset)))
     {
         return res;
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 3ad3505..6cd8443 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -6,29 +6,29 @@
 void (sv_proc_t::WRITE_FRD)(float32_t value)
 {
     fprintf(stderr, "WRITE_FRD float32_t %f\n", (float)value.v);
-    DO_WRITE_FREG( _insn->rd().reg, freg(value) );
+    DO_WRITE_FREG( _insn->rd(), freg(value) );
 }
 
 void (sv_proc_t::WRITE_FRD)(float64_t value)
 {
     fprintf(stderr, "WRITE_FRD float64_t %g\n", (double)value.v);
-    DO_WRITE_FREG( _insn->rd().reg, freg(value) );
+    DO_WRITE_FREG( _insn->rd(), freg(value) );
 }
 
 void (sv_proc_t::WRITE_FRD)(freg_t value)
 {
     fprintf(stderr, "WRITE_FRD fsv_reg_t %lx\n", value.v[0]);
-    DO_WRITE_FREG( _insn->rd().reg, freg(value) );
+    DO_WRITE_FREG( _insn->rd(), freg(value) );
 }
 
 void (sv_proc_t::WRITE_RVC_FRS2S)(float32_t value)
 {
-    WRITE_FREG(_insn->rvc_rs2s().reg, freg(value));
+    WRITE_FREG(_insn->rvc_rs2s(), freg(value));
 }
 
 void (sv_proc_t::WRITE_RVC_FRS2S)(float64_t const& value)
 {
-    WRITE_FREG(_insn->rvc_rs2s().reg, freg(value));
+    WRITE_FREG(_insn->rvc_rs2s(), freg(value));
 }
 
 //void (sv_proc_t::WRITE_RD)(bool value)
@@ -79,13 +79,24 @@ void (sv_proc_t::WRITE_RD)(sv_reg_t const& value)
 //    STATE.XPR.write(reg, value);
 //}
 
+void (sv_proc_t::DO_WRITE_FREG)(reg_spec_t const& spec, freg_t const& value)
+{
+    //WRITE_REG( reg, value ); // XXX TODO: replace properly
+    reg_t reg = spec.reg;
+    if (spec.offset) {
+        reg += *spec.offset;
+    }
+    STATE.FPR.write(reg, value);
+    dirty_fp_state;
+}
+
 void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value)
 {
     //WRITE_REG( reg, value ); // XXX TODO: replace properly
     reg_t reg = spec.reg;
-    //if (spec.offset) {
-    //    reg += *spec.offset;
-    //}
+    if (spec.offset) {
+        reg += *spec.offset;
+    }
     STATE.XPR.write(reg, value);
 }
 
@@ -107,13 +118,23 @@ void (sv_proc_t::WRITE_RD)(uint_fast64_t value)
 }
 */
 
+freg_t (sv_proc_t::READ_FREG)(reg_spec_t const& spec)
+{
+    reg_t reg = spec.reg;
+    uint8_t elwidth = _insn->reg_elwidth(reg, true);
+    if (spec.offset && spec.reg != 2) {
+        reg += *spec.offset;
+    }
+    return _insn->p->get_state()->FPR[reg]; // XXX TODO: offset
+}
+
 reg_t (sv_proc_t::READ_REG)(reg_spec_t const& spec)
 {
     reg_t reg = spec.reg;
     uint8_t elwidth = _insn->reg_elwidth(reg, true);
-    //if (spec.offset) {
-    //    reg += *spec.offset;
-    //}
+    if (spec.offset && spec.reg != 2) {
+        reg += *spec.offset;
+    }
     return _insn->p->get_state()->XPR[reg]; // XXX TODO: offset
 }
 
@@ -147,27 +168,27 @@ sv_reg_t sv_proc_t::get_rvc_sp()
 freg_t sv_proc_t::get_frs1()
 {
     reg_spec_t spec = _insn->rs1();
-    return READ_FREG(spec.reg);
+    return READ_FREG(spec);
 }
 
 freg_t sv_proc_t::get_frs3()
 {
-    return READ_FREG(_insn->rs3().reg);
+    return READ_FREG(_insn->rs3());
 }
 
 freg_t sv_proc_t::get_frs2()
 {
-    return READ_FREG(_insn->rs2().reg);
+    return READ_FREG(_insn->rs2());
 }
 
 freg_t sv_proc_t::get_rvc_frs2s()
 {
-    return READ_FREG(_insn->rvc_rs2s().reg);
+    return READ_FREG(_insn->rvc_rs2s());
 }
 
 freg_t sv_proc_t::get_rvc_frs2()
 {
-    return READ_FREG(_insn->rvc_rs2().reg);
+    return READ_FREG(_insn->rvc_rs2());
 }
 
 sv_reg_t sv_proc_t::get_shamt()
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 39dc5e1..11537f3 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -25,6 +25,8 @@
 #undef WRITE_RVC_FRS2S
 #undef WRITE_RD
 #undef READ_REG
+#undef READ_FREG
+#undef DO_WRITE_FREG
 #undef RVC_SP
 #undef SHAMT
 #undef sext_xlen
@@ -72,12 +74,14 @@ public:
     void (WRITE_RVC_RS1S)(sv_reg_t const& value); // XXX TODO investigate
     //void (WRITE_RVC_RS1S)(sv_sreg_t value); // XXX TODO investigate
     //void (WRITE_REG)(reg_t reg, uint64_t value);
+    void (DO_WRITE_FREG)(reg_spec_t const&reg, freg_t const& value);
     void (WRITE_REG)(reg_spec_t const&reg, sv_reg_t const& value);
     //void (WRITE_REG)(reg_t reg, sv_sreg_t value);
     void (WRITE_FRD)(freg_t value);
     void (WRITE_FRD)(float64_t value);
     void (WRITE_FRD)(float32_t value);
     reg_t (READ_REG)(reg_spec_t const& i);
+    freg_t (READ_FREG)(reg_spec_t const& i);
 
     processor_t *p;
     sv_insn_t *_insn;