From: Samuel Pitoiset Date: Wed, 8 Jul 2020 11:12:37 +0000 (+0200) Subject: radv: set depth/stencil enable values correctly for the meta clear path X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84ed2793ebdd2e5d60edc62abdef2881e703055c;p=mesa.git radv: set depth/stencil enable values correctly for the meta clear path They are booleans. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index fa3832e70ea..4d4dd109165 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -664,11 +664,11 @@ create_depthstencil_pipeline(struct radv_device *device, const VkPipelineDepthStencilStateCreateInfo ds_state = { .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO, - .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT), + .depthTestEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT), .depthCompareOp = VK_COMPARE_OP_ALWAYS, - .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT), + .depthWriteEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT), .depthBoundsTestEnable = false, - .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT), + .stencilTestEnable = !!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT), .front = { .passOp = VK_STENCIL_OP_REPLACE, .compareOp = VK_COMPARE_OP_ALWAYS,