From: lkcl Date: Tue, 14 Jun 2022 15:45:06 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~1787 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84f08e3b0779c91db547fcdd12fe8acb3dbd1f5d;p=libreriscv.git --- diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn index d18899d44..bee79fcd3 100644 --- a/openpower/sv/mv.swizzle.mdwn +++ b/openpower/sv/mv.swizzle.mdwn @@ -170,6 +170,9 @@ the end. If no marker is present then the destination subvector length may be assumed to be 4. SUBVL is considered to be the "source" subvector length. +Pseudocode exploiting python "yield" for clarity: element-width overrides, +Saturation and Predication also left out, for clarity: + ``` def index_src(): for i in range(VL): @@ -183,7 +186,6 @@ length. else: yield (i*SUBVL, swiz[j]-3) - # yield an outer-SUBVL, inner VL loop with DEST SUBVL def index_dest(): for i in range(VL): for j in range(dst_subvl):