From: Staf Verhaegen <staf@stafverhaegen.be>
Date: Mon, 25 Jun 2018 16:48:03 +0000 (+0200)
Subject: Don't use tri-state logic for TDO; introduce TDO_EN signal to indicate when TDO is... 
X-Git-Tag: 24jan2021ls180~58
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84f13c8e9898b63b686c4c5e982f6ef5e554a7c6;p=c4m-jtag.git

Don't use tri-state logic for TDO; introduce TDO_EN signal to indicate when TDO is valid.

Add assert for conflicting TDO assignment.
---

diff --git a/rtl/vhdl/c4m_jtag_idblock.vhdl b/rtl/vhdl/c4m_jtag_idblock.vhdl
index d4353c1..4c06bef 100644
--- a/rtl/vhdl/c4m_jtag_idblock.vhdl
+++ b/rtl/vhdl/c4m_jtag_idblock.vhdl
@@ -18,6 +18,7 @@ entity c4m_jtag_idblock is
     TCK:        in std_logic;
     TDI:        in std_logic;
     TDO:        out std_logic;
+    TDO_EN:     out std_logic := '0';
 
     -- JTAG state
     STATE:      in TAPSTATE_TYPE;
@@ -65,5 +66,7 @@ begin
 
   EN_TDO <= STATE = Shift and DRSTATE = '1' and (IR = CMD_IDCODE or IR = CMD_BYPASS);
   TDO <= SR_ID(0) when EN_TDO else
-         'Z';
+         '0';
+  TDO_EN <= '1' when EN_TDO else
+            '0';
 end rtl;
diff --git a/rtl/vhdl/c4m_jtag_ioblock.vhdl b/rtl/vhdl/c4m_jtag_ioblock.vhdl
index ec63440..c70be6f 100644
--- a/rtl/vhdl/c4m_jtag_ioblock.vhdl
+++ b/rtl/vhdl/c4m_jtag_ioblock.vhdl
@@ -15,6 +15,7 @@ entity c4m_jtag_ioblock is
     TCK:        in std_logic;
     TDI:        in std_logic;
     TDO:        out std_logic;
+    TDO_EN:     out std_logic := '0';
 
     -- JTAG state
     STATE:      in TAPSTATE_TYPE;
@@ -84,5 +85,7 @@ begin
                 SR_Normal;
 
   TDO <= BDSR_OUT(0) when ISSAMPLECMD and STATE = Shift else
-         'Z';
+         '0';
+  TDO_EN <= '1' when ISSAMPLECMD and STATE = Shift else
+            '0';
 end rtl;
diff --git a/rtl/vhdl/c4m_jtag_irblock.vhdl b/rtl/vhdl/c4m_jtag_irblock.vhdl
index e8b34a5..8be483a 100644
--- a/rtl/vhdl/c4m_jtag_irblock.vhdl
+++ b/rtl/vhdl/c4m_jtag_irblock.vhdl
@@ -14,6 +14,7 @@ entity c4m_jtag_irblock is
     TCK:        in std_logic;
     TDI:        in std_logic;
     TDO:        out std_logic;
+    TDO_EN:     out std_logic := '0';
     
     -- JTAG state
     STATE:      in TAPSTATE_TYPE;
@@ -57,5 +58,7 @@ begin
   end process;
 
   TDO <= SHIFT_IR(0) when STATE = Shift and IRSTATE = '1' else
-         'Z';
+         '0';
+  TDO_EN <= '1' when STATE = Shift and IRSTATE = '1' else
+            '0';
 end rtl;
diff --git a/rtl/vhdl/c4m_jtag_pkg.vhdl b/rtl/vhdl/c4m_jtag_pkg.vhdl
index 87771f2..e009d23 100644
--- a/rtl/vhdl/c4m_jtag_pkg.vhdl
+++ b/rtl/vhdl/c4m_jtag_pkg.vhdl
@@ -52,6 +52,7 @@ package c4m_jtag is
       TCK:      in std_logic;
       TDI:      in std_logic;
       TDO:      out std_logic;
+      TDO_EN:   out std_logic;
     
       -- JTAG state
       STATE:    in TAPSTATE_TYPE;
@@ -76,6 +77,7 @@ package c4m_jtag is
       TCK:      in std_logic;
       TDI:      in std_logic;
       TDO:      out std_logic;
+      TDO_EN:   out std_logic;
 
       -- JTAG state
       STATE:    in TAPSTATE_TYPE;
@@ -120,6 +122,7 @@ package c4m_jtag is
       TCK:      in std_logic;
       TDI:      in std_logic;
       TDO:      out std_logic;
+      TDO_EN:   out std_logic;
 
       -- JTAG state
       STATE:    in TAPSTATE_TYPE;
@@ -154,6 +157,7 @@ package c4m_jtag is
       TMS:      in std_logic;
       TDI:      in std_logic;
       TDO:      out std_logic;
+      TDO_EN:   out std_logic;
       TRST_N:   in std_logic;
 
       -- The FSM state indicators
diff --git a/rtl/vhdl/c4m_jtag_tap_controller.vhdl b/rtl/vhdl/c4m_jtag_tap_controller.vhdl
index a6f0f15..5c2d6dc 100644
--- a/rtl/vhdl/c4m_jtag_tap_controller.vhdl
+++ b/rtl/vhdl/c4m_jtag_tap_controller.vhdl
@@ -19,6 +19,7 @@ entity c4m_jtag_tap_controller is
     TMS:        in std_logic;
     TDI:        in std_logic;
     TDO:        out std_logic;
+    TDO_EN:     out std_logic;
     TRST_N:     in std_logic;
 
     -- The FSM state indicators
@@ -44,10 +45,18 @@ end c4m_jtag_tap_controller;
 architecture rtl of c4m_jtag_tap_controller is
   signal S_STATE:       TAPSTATE_TYPE;
   signal S_NEXT_STATE:  TAPSTATE_TYPE;
-  signal S_IRSTATE:       std_logic;
-  signal S_DRSTATE:       std_logic;
+  signal S_IRSTATE:     std_logic;
+  signal S_DRSTATE:     std_logic;
   signal S_IR:          std_logic_vector(IR_WIDTH-1 downto 0);
 
+  signal IR_TDO:        std_logic;
+  signal IR_TDO_EN:     std_logic;
+  signal ID_TDO:        std_logic;
+  signal ID_TDO_EN:     std_logic;
+  signal IO_TDO:        std_logic;
+  signal IO_TDO_EN:     std_logic;
+  signal EN:            std_logic_vector(2 downto 0) := "000";
+
   -- TODO: Automate PART_NUMBER generation
   constant PART_NUMBER: std_logic_vector(15 downto 0) := "0000000010001001";
   -- TODO: Get manufacturer ID
@@ -78,7 +87,8 @@ begin
     port map (
       TCK => TCK,
       TDI => TDI,
-      TDO => TDO,
+      TDO => IR_TDO,
+      TDO_EN => IR_TDO_EN,
       STATE => S_STATE,
       NEXT_STATE => S_NEXT_STATE,
       IRSTATE => S_IRSTATE,
@@ -95,7 +105,8 @@ begin
     port map (
       TCK => TCK,
       TDI => TDI,
-      TDO => TDO,
+      TDO => ID_TDO,
+      TDO_EN => ID_TDO_EN,
       STATE => S_STATE,
       NEXT_STATE => S_NEXT_STATE,
       DRSTATE => S_DRSTATE,
@@ -111,7 +122,8 @@ begin
     port map (
       TCK => TCK,
       TDI => TDI,
-      TDO => TDO,
+      TDO => IO_TDO,
+      TDO_EN => IO_TDO_EN,
       STATE => S_STATE,
       NEXT_STATE => S_NEXT_STATE,
       DRSTATE => S_DRSTATE,
@@ -123,6 +135,17 @@ begin
       PAD_IN => PAD_IN,
       PAD_EN => PAD_EN
     );
+
+  TDO <= IR_TDO when IR_TDO_EN = '1' else
+         ID_TDO when ID_TDO_EN = '1' else
+         IO_TDO when IO_TDO_EN = '1' else
+         '0';
+  TDO_EN <= IR_TDO_EN or ID_TDO_EN or IO_TDO_EN;
+
+  EN <= IR_TDO_EN & ID_TDO_EN & IO_TDO_EN;
+  assert EN = "000" or EN = "100" or EN = "010" or EN = "001"
+    report "TDO conflict in c4m_jtag_tap_controller"
+    severity ERROR;
 end rtl;