From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Oct 2018 11:26:47 +0000 (+0100)
Subject: debug print for floating-point regs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84f44054522cb88e7ba81d5c61f09b4e5523b992;p=riscv-isa-sim.git

debug print for floating-point regs
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 2feaf48..7e98462 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -55,9 +55,16 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
       if (vlen > 1)
       {
+#if defined(USING_REG_RD)
         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs), READ_REG(insn._rd()));
+#endif
+#if defined(USING_REG_FRD)
+        fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
+                xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
+                dest_pred & (1<<voffs), READ_FREG(insn._rd()));
+#endif
       }
       insn.reset_caches(); // ready to increment offsets in next iteration
       if (insn.stop_vloop())