From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 27 May 2019 10:25:18 +0000 (+0200)
Subject: Give error instead of asserting for invalid range, fixes #947
X-Git-Tag: yosys-0.9~105^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84ffb217081fed7ddf1f683f65f2a2fdf813cd6b;p=yosys.git

Give error instead of asserting for invalid range, fixes #947
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 379fed641..1b19ba4e5 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -904,7 +904,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			if (!range_valid)
 				log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str());
 
-			log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
+			if (!(range_left >= range_right || (range_left == -1 && range_right == 0)))
+				log_file_error(filename, linenum, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
 
 			RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
 			wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);