From: Clifford Wolf Date: Sat, 18 Oct 2014 13:20:38 +0000 (+0200) Subject: Fixed various VS warnings X-Git-Tag: yosys-0.4~32 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=84ffe04075bbddfd1b288295c07d036416923c3a;p=yosys.git Fixed various VS warnings --- diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 70976b68b..e2d63de60 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2457,7 +2457,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) } log_assert(block != NULL); - log_assert(variables.count(str)); + log_assert(variables.count(str) != 0); while (!block->children.empty()) { diff --git a/kernel/log.cc b/kernel/log.cc index 19eb38c73..807f58bf6 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -64,7 +64,7 @@ int gettimeofday(struct timeval *tv, struct timezone *tz) counter.QuadPart *= 1000000; counter.QuadPart /= freq.QuadPart; - tv->tv_sec = counter.QuadPart / 1000000; + tv->tv_sec = long(counter.QuadPart / 1000000); tv->tv_usec = counter.QuadPart % 1000000; return 0; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 36443c5ac..1a9eb4d14 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1778,7 +1778,7 @@ const std::map &RTLIL::Cell::connections() cons bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const { - return parameters.count(paramname); + return parameters.count(paramname) != 0; } void RTLIL::Cell::unsetParam(RTLIL::IdString paramname) @@ -3041,7 +3041,7 @@ bool RTLIL::SigSpec::parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, R if (lhs.chunks_.size() == 1) { char *p = (char*)str.c_str(), *endptr; - long long int val = strtoll(p, &endptr, 10); + long int val = strtol(p, &endptr, 10); if (endptr && endptr != p && *endptr == 0) { sig = RTLIL::SigSpec(val, lhs.width_); cover("kernel.rtlil.sigspec.parse.rhs_dec"); diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 7d1d273cb..f314f546a 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -231,7 +231,7 @@ std::string make_temp_file(std::string template_str) while (1) { for (int i = 0; i < 6; i++) { static std::string y = "0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"; - static uint32_t x = 314159265 ^ time(NULL); + static uint32_t x = 314159265 ^ uint32_t(time(NULL)); x ^= x << 13, x ^= x >> 17, x ^= x << 5; template_str[pos+i] = y[x % y.size()]; } diff --git a/libs/ezsat/ezsat.cc b/libs/ezsat/ezsat.cc index 657bed9d2..b713c4c91 100644 --- a/libs/ezsat/ezsat.cc +++ b/libs/ezsat/ezsat.cc @@ -1118,7 +1118,7 @@ int64_t ezSAT::vec_model_get_signed(const std::vector &modelExpressions, co for (int i = 0; i < 64; i++) { int j = i < int(vec1.size()) ? i : vec1.size()-1; if (modelMap.at(vec1[j])) - value |= 1 << i; + value |= int64_t(1) << i; } return value; } @@ -1132,7 +1132,7 @@ uint64_t ezSAT::vec_model_get_unsigned(const std::vector &modelExpressions, modelMap[modelExpressions[i]] = modelValues[i]; for (int i = 0; i < int(vec1.size()); i++) if (modelMap.at(vec1[i])) - value |= 1 << i; + value |= uint64_t(1) << i; return value; } diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 4194f88c3..8a20898cf 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -112,7 +112,7 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo if (regs.check_any(s1) != regs.check_any(s2)) return regs.check_any(s2); if (direct_wires.count(w1) != direct_wires.count(w2)) - return direct_wires.count(w2); + return direct_wires.count(w2) != 0; if (conns.check_any(s1) != conns.check_any(s2)) return conns.check_any(s2); } diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 354586937..2496f15d3 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -747,7 +747,7 @@ struct ShareWorker forbidden_controls_cache[cell].insert(bits.begin(), bits.end()); } - log_assert(recursion_state.count(cell)); + log_assert(recursion_state.count(cell) != 0); recursion_state.erase(cell); return forbidden_controls_cache[cell]; @@ -862,7 +862,7 @@ struct ShareWorker activation_patterns_cache[cell].insert(c_patterns.begin(), c_patterns.end()); } - log_assert(recursion_state.count(cell)); + log_assert(recursion_state.count(cell) != 0); recursion_state.erase(cell); optimize_activation_patterns(activation_patterns_cache[cell]); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 510dcd60b..a02eafb96 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -108,7 +108,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool LibertyAst *best_cell = NULL; std::map best_cell_ports; int best_cell_pins = 0; - float best_cell_area = 0; + double best_cell_area = 0; if (ast->id != "library") log_error("Format error in liberty file.\n"); @@ -144,7 +144,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool this_cell_ports[cell_rst_pin] = 'R'; this_cell_ports[cell_next_pin] = 'D'; - float area = 0; + double area = 0; LibertyAst *ar = cell->find("area"); if (ar != NULL && !ar->value.empty()) area = atof(ar->value.c_str()); @@ -204,7 +204,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo LibertyAst *best_cell = NULL; std::map best_cell_ports; int best_cell_pins = 0; - float best_cell_area = 0; + double best_cell_area = 0; if (ast->id != "library") log_error("Format error in liberty file.\n"); @@ -236,7 +236,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo this_cell_ports[cell_clr_pin] = 'R'; this_cell_ports[cell_next_pin] = 'D'; - float area = 0; + double area = 0; LibertyAst *ar = cell->find("area"); if (ar != NULL && !ar->value.empty()) area = atof(ar->value.c_str());