From: Luke Kenneth Casson Leighton Date: Wed, 27 Jul 2022 01:03:53 +0000 (+0100) Subject: mention RVV has Silicon-partner choice of MAXVL X-Git-Tag: opf_rfc_ls005_v1~1022 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85036b270568b77c4eb32d5ed955f893dd0ad696;p=libreriscv.git mention RVV has Silicon-partner choice of MAXVL --- diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index 5421bb38f..ec8165822 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -30,7 +30,7 @@ * (16): [AVX512 Wikipedia](https://en.wikipedia.org/wiki/AVX-512), [Lifecycle of an instruction set](https://media.handmade-seattle.com/tom-forsyth/) including full slides * (17): difficult to exactly ascertain, contains subsets. Critically depends on ISA support from earlier x86 ISA subsets (several more thousand instructions). See [SIMD ISA listing](https://www.officedaytime.com/simd512e/) * (18): [RVV Spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc) -* (19): Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction). +* (19): Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction). However, like SVE2, the Maximum Vector length is a Silicon-partner choice, which creates similar limitations that SVP64 does not have. * (20): like SVP64 it is up to the hardware implementor to choose whether to support 128-bit elements. * (21): [NEC SX Aurora](https://ftp.libre-soc.org/NEC_SX_Aurora_TSUBASA_VectorEngine-as-manual-v1.2.pdf) is based on the original Cray Vectors * (22): [Aurora ISA guide](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf) Appendix-3 11.1 p508