From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 9 Oct 2012 17:07:53 +0000 (+0200)
Subject: bank: remove RE signal for field registers
X-Git-Tag: 24jan2021_ls180~2099^2~828
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85081793cf5c43ed3a602a8ce8a709ae5b1a9518;p=litex.git

bank: remove RE signal for field registers
---

diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
index 140e9baa..b49ea56a 100644
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@@ -29,7 +29,6 @@ class Bank:
 					self.interface.we & \
 					(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
 			elif isinstance(reg, RegisterFields):
-				sync.append(reg.re.eq(0))
 				bwra = [Constant(i, BV(nbits))]
 				offset = 0
 				for field in reg.fields:
@@ -37,7 +36,6 @@ class Bank:
 						bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
 					offset += field.size
 				if len(bwra) > 1:
-					bwra.append(reg.re.eq(1))
 					bwcases.append(bwra)
 				# commit atomic writes
 				for field in reg.fields:
diff --git a/migen/bank/description.py b/migen/bank/description.py
index 854e19d6..a83d87d6 100644
--- a/migen/bank/description.py
+++ b/migen/bank/description.py
@@ -28,13 +28,9 @@ class Field:
 				self.we = Signal()
 
 class RegisterFields:
-	def __init__(self, name, fields, re=None):
+	def __init__(self, name, fields):
 		self.name = name
 		self.fields = fields
-		if re is None:
-			self.re = Signal()
-		else:
-			self.re = re
 
 class RegisterField(RegisterFields):
 	def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False):
@@ -111,7 +107,7 @@ def expand_description(description, busword):
 				else:
 					f.append(field)
 			if f:
-				d.append(RegisterFields(reg.name, f, reg.re))
+				d.append(RegisterFields(reg.name, f))
 		else:
 			raise TypeError
 	return d