From: Tim Newsome <tim@sifive.com>
Date: Wed, 4 May 2016 16:45:56 +0000 (-0700)
Subject: Use fence.i in Debug ROM.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=850e745dcf300cd5369d006b31e17ebfb417eab4;p=riscv-isa-sim.git

Use fence.i in Debug ROM.

This replaces a hack that just disabled all of the icache.
---

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index e7e99d0..c164eeb 100755
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -87,6 +87,7 @@ _entry:
 
 jdebugram:
         # Save s1 so that the debug program can use two registers.
+        fence.i
         csrr    s0, CSR_MISA
         bltz    s0, save_not_32
 save_32:
diff --git a/debug_rom/debug_rom.h b/debug_rom/debug_rom.h
index 42fda2b..c429b22 100644
--- a/debug_rom/debug_rom.h
+++ b/debug_rom/debug_rom.h
@@ -6,14 +6,14 @@ static const unsigned char debug_rom_raw[] = {
   0x93, 0x94, 0x14, 0x00, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x34, 0x80, 0x43,
   0x6f, 0x00, 0xc0, 0x00, 0x13, 0x00, 0x00, 0x00, 0x23, 0x2e, 0x80, 0x42,
   0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x84, 0x00, 0x63, 0x04, 0x04, 0x00,
-  0x6f, 0x00, 0x40, 0x05, 0x73, 0x24, 0x20, 0x79, 0x73, 0x00, 0x20, 0x79,
+  0x6f, 0x00, 0x80, 0x05, 0x73, 0x24, 0x20, 0x79, 0x73, 0x00, 0x20, 0x79,
   0x73, 0x10, 0x24, 0x79, 0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x74, 0x00,
-  0x13, 0x04, 0xd4, 0xff, 0x63, 0x16, 0x04, 0x02, 0x73, 0x24, 0x00, 0xf1,
-  0x63, 0x46, 0x04, 0x00, 0x23, 0x2e, 0x90, 0x42, 0x67, 0x00, 0x00, 0x40,
-  0x13, 0x14, 0x14, 0x00, 0x63, 0x46, 0x04, 0x00, 0x23, 0x3c, 0x90, 0x42,
-  0x67, 0x00, 0x00, 0x40, 0x13, 0x00, 0x00, 0x00, 0x67, 0x00, 0x00, 0x40,
-  0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10, 0x73, 0x60, 0x04, 0x79,
-  0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x04, 0x40, 0xe3, 0x0c, 0x04, 0xfe,
-  0x6f, 0xf0, 0x1f, 0xfc
+  0x13, 0x04, 0xd4, 0xff, 0x63, 0x18, 0x04, 0x02, 0x0f, 0x10, 0x00, 0x00,
+  0x73, 0x24, 0x00, 0xf1, 0x63, 0x46, 0x04, 0x00, 0x23, 0x2e, 0x90, 0x42,
+  0x67, 0x00, 0x00, 0x40, 0x13, 0x14, 0x14, 0x00, 0x63, 0x46, 0x04, 0x00,
+  0x23, 0x3c, 0x90, 0x42, 0x67, 0x00, 0x00, 0x40, 0x13, 0x00, 0x00, 0x00,
+  0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10,
+  0x73, 0x60, 0x04, 0x79, 0x73, 0x24, 0x00, 0x79, 0x13, 0x74, 0x04, 0x40,
+  0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0xdf, 0xfb
 };
-static const unsigned int debug_rom_raw_len = 184;
+static const unsigned int debug_rom_raw_len = 188;
diff --git a/riscv/mmu.h b/riscv/mmu.h
index 8fe3043..a87b6af 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -117,7 +117,6 @@ public:
       entry->tag = -1;
       tracer.trace(paddr, length, FETCH);
     }
-    entry->tag = -1;    // TODO: this is hack to work around Debug RAM code being cached
     return entry;
   }