From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 18 Mar 2021 21:26:04 +0000 (+0000)
Subject: more hint/comments
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=851647bf589fe848574ad35a3a225fe5a49a54d9;p=soc.git

more hint/comments
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index e5ece6de..3e7cd22b 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -272,7 +272,8 @@ class TestIssuerInternal(Elaboratable):
         or CRRegs r_ports['pred'].  in the case of CRs it will have to
         be done through multiple reads, extracting one relevant at a time.
         later, a faster way would be to use the 32-bit-wide CR port but
-        this is more complex decoding, here.
+        this is more complex decoding, here.  equivalent code used in
+        ISACaller is "from soc.decoder.isa.caller import get_predcr"
         """
         comb = m.d.comb
         sync = m.d.sync