From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 12 Dec 2021 13:15:51 +0000 (+0000)
Subject: in a terrible botched way, get at I-Cache and set it up
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=851fb74227bd24582e7a208cb9f094940eec0dbc;p=soc.git

in a terrible botched way, get at I-Cache and set it up
this is for adding in I-Cache and MMU into core.
---

diff --git a/src/soc/config/ifetch.py b/src/soc/config/ifetch.py
index b33d7464..35a9ddec 100644
--- a/src/soc/config/ifetch.py
+++ b/src/soc/config/ifetch.py
@@ -20,9 +20,11 @@ class ConfigFetchUnit:
                   }
         self.pspec = pspec
         if self.pspec.imem_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
-            self.fu = self.lsmem.lsi.icache # ICache already FetchUnitInterface
+            # XXX BLECH! use pspec to transfer the I-Cache which is
+            # created down inside LoadStore1!
+            self.fu = icache = pspec.icache # ICache already FetchUnitInterface
             # tell I-Cache to connect up to its FetchUnitInterface
-            self.fu.use_fetch_interface()
+            icache.use_fetch_interface()
             return
 
         fukls = fudict[pspec.imem_ifacetype]
diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index cb42f1b6..f66e2210 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -890,7 +890,6 @@ class ICache(FetchUnitInterface, Elaboratable):
         if hasattr(ibus, "stall"):
             comb += self.bus.stall.eq(ibus.stall)
 
-
         return m
 
 
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 1d8d3d72..6bca3bd8 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -156,6 +156,8 @@ class NonProductionCore(ControlBase):
             lsi = l0.cmpi.lsmem.lsi # a LoadStore1 Interface object
             print ("core lsmem.lsi", lsi)
             mmu.alu.set_ldst_interface(lsi)
+            # urr store I-Cache in core so it is easier to get at
+            self.icache = lsi.icache
 
         # register files (yes plural)
         self.regs = RegFiles(pspec, make_hazard_vecs=self.make_hazard_vecs)
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 6aa79019..9c40e45d 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -48,7 +48,7 @@ from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
 from soc.clock.select import ClockSelect
 from soc.clock.dummypll import DummyPLL
 from openpower.sv.svstate import SVSTATERec
-
+from soc.experiment.icache import ICache
 
 from nmutil.util import rising_edge
 
@@ -433,6 +433,10 @@ class TestIssuerInternal(Elaboratable):
             self.svp64 = SVP64PrefixDecoder()  # for decoding SVP64 prefix
 
         # Test Instruction memory
+        if hasattr(core, "icache"):
+            # XXX BLECH! use pspec to transfer the I-Cache to ConfigFetchUnit
+            # truly dreadful.  needs a huge reorg.
+            pspec.icache = core.icache
         self.imem = ConfigFetchUnit(pspec).fu
 
         # DMI interface
@@ -1017,7 +1021,10 @@ class TestIssuerInternal(Elaboratable):
         dbd = DomainRenamer(self.dbg_domain)
 
         m.submodules.core = core = csd(self.core)
-        m.submodules.imem = imem = csd(self.imem)
+        # this _so_ needs sorting out.  ICache is added down inside
+        # LoadStore1 and is already a submodule of LoadStore1
+        if not isinstance(self.imem, ICache):
+            m.submodules.imem = imem = csd(self.imem)
         m.submodules.dbg = dbg = dbd(self.dbg)
         if self.jtag_en:
             m.submodules.jtag = jtag = dbd(self.jtag)