From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 22 Sep 2015 12:33:44 +0000 (+0800)
Subject: sim: fix slice assign
X-Git-Tag: 24jan2021_ls180~2099^2~3^2~47
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8534562185cd9297b8aafe21076df1d8f0c99ffb;p=litex.git

sim: fix slice assign
---

diff --git a/migen/sim/core.py b/migen/sim/core.py
index c9da09cc..e9d3c560 100644
--- a/migen/sim/core.py
+++ b/migen/sim/core.py
@@ -162,13 +162,13 @@ class Evaluator:
                 self.assign(element, value & (2**nbits-1))
                 value >>= nbits
         elif isinstance(node, _Slice):
-            full_value = self.eval(node, True)
+            full_value = self.eval(node.value, True)
             # clear bits assigned to by the slice
             full_value &= ~((2**node.stop-1) - (2**node.start-1))
             # set them to the new value
             value &= 2**(node.stop - node.start)-1
             full_value |= value << node.start
-            self.assign(node, full_value)
+            self.assign(node.value, full_value)
         elif isinstance(node, _ArrayProxy):
             self.assign(node.choices[self.eval(node.key)], value)
         elif isinstance(node, _MemoryLocation):