From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 25 Jul 2016 14:39:25 +0000 (+0200)
Subject: Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
X-Git-Tag: yosys-0.7~159
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8537c4d2061db1ee11defc357781c6c534be5b3d;p=yosys.git

Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
---

diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index 430425ea8..556e8b826 100644
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -158,7 +158,7 @@ void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 PRIVATE_NAMESPACE_END
 
-bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_cell(RTLIL::Cell *cell)
+bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
 {
 	if (cell->type.in("$not", "$pos")) {
 		bitwise_unary_op(this, cell);
diff --git a/kernel/celledges.h b/kernel/celledges.h
index e2cc408d7..6aab9ed43 100644
--- a/kernel/celledges.h
+++ b/kernel/celledges.h
@@ -29,7 +29,7 @@ struct AbstractCellEdgesDatabase
 {
 	virtual ~AbstractCellEdgesDatabase() { }
 	virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;
-	bool add_cell(RTLIL::Cell *cell);
+	bool add_edges_from_cell(RTLIL::Cell *cell);
 };
 
 struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 8e9dc3112..19fad01ef 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -344,7 +344,7 @@ static void run_edges_test(RTLIL::Design *design, bool verbose)
 	SatGen satgen(&ez, &sigmap);
 
 	FwdCellEdgesDatabase edges_db(sigmap);
-	if (!edges_db.add_cell(cell))
+	if (!edges_db.add_edges_from_cell(cell))
 		log_error("Creating edge database failed for this cell!\n");
 
 	dict<SigBit, pool<SigBit>> satgen_db;