From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 18 Jun 2019 12:39:46 +0000 (+0100)
Subject: add separate read/write port
X-Git-Tag: div_pipeline~1839
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=853a2ec703071117232ae0397700235a79ec6f2f;p=soc.git

add separate read/write port
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 186108dc..11744db2 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -28,20 +28,27 @@ class TestMemory(Elaboratable):
     def __init__(self, regwid, addrw):
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
-        self.adr   = Signal(addrw)
+        self.adr_r  = Signal(addrw)
         self.dat_r = Signal(regwid)
+        self.adr_w  = Signal(addrw)
         self.dat_w = Signal(regwid)
         self.we    = Signal()
+        self.re    = Signal()
         self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
 
     def elaborate(self, platform):
         m = Module()
         m.submodules.rdport = rdport = self.mem.read_port()
         m.submodules.wrport = wrport = self.mem.write_port()
+        # read port
         m.d.comb += [
-            rdport.addr.eq(self.adr[self.ddepth:]), # ignore low bits
+            rdport.addr.eq(self.adr_r[self.ddepth:]), # ignore low bits
+            rdport.en.eq(self.re),
             self.dat_r.eq(rdport.data),
-            wrport.addr.eq(self.adr),
+        ]
+        # write port
+        m.d.comb += [
+            wrport.addr.eq(self.adr_w),
             wrport.data.eq(self.dat_w),
             wrport.en.eq(self.we),
         ]
@@ -1151,7 +1158,7 @@ def scoreboard_sim(dut, alusim):
             instrs = create_random_ops(dut, 15, True, 4)
 
         if True: # LD/ST test (with immediate)
-            instrs.append( (1, 2, 2, 0x10, 1, 1, (0, 0)) )
+            instrs.append( (1, 2, 2, 0x30, 1, 1, (0, 0)) )
             #instrs.append( (1, 2, 7, 0x10, 1, 1, (0, 0)) )
 
         if False: