From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 17 Jun 2021 18:43:00 +0000 (+0100)
Subject: add SVP64REMAP Record
X-Git-Tag: xlen-bcd~435
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85424cf44d01b92e064248c2944d01680700e99b;p=openpower-isa.git

add SVP64REMAP Record
https://libre-soc.org/openpower/sv/remap/
---

diff --git a/src/openpower/sv/svp64.py b/src/openpower/sv/svp64.py
index 634687e2..8c7a1963 100644
--- a/src/openpower/sv/svp64.py
+++ b/src/openpower/sv/svp64.py
@@ -8,7 +8,9 @@ For full spec see https://libre-soc.org/openpower/sv/
 
 from nmigen import Record
 
+
 # in nMigen, Record begins at the LSB and fills upwards
+# however in OpenPOWER, numbering is MSB0.  sigh.
 class SVP64Rec(Record):
     """SVP64 RM (Remap) Record.
 
@@ -35,5 +37,36 @@ class SVP64Rec(Record):
 
     def ports(self):
         return [self.mmode, self.mask, self.elwidth, self.ewsrc,
-                self.extra, self.mode]
+                self.subvl, self.extra, self.mode]
+
+
+# in nMigen, Record begins at the LSB and fills upwards
+# however in OpenPOWER, numbering is MSB0.  sigh.
+class SVP64REMAP(Record):
+    """SVP64 SHAPE (REMAP) Record.
+
+    https://libre-soc.org/openpower/sv/remap/
+
+    | Field Name  | Field bits | Description                            |
+    |-------------|------------|----------------------------------------|
+    | XDIMSZ      | `0:5`      | X Dimension size                       |
+    | YDIMSZ      | `6:11`     | Y Dimension size                       |
+    | ZDIMSZ      | `12:17`    | Z Dimension size                       |
+    | PERMUTE     | `18:20`    | Permutation order (XYZ, XZY, YXZ...)   |
+    | INVXYZ      | `21:23`    | Invert order of X or Y or Z            |
+    | OFFSET      | `24:29`    | Adds to index before modulo            |
+    | APPLYDIM    | `30:31`    | how many dimensions in use             |
+    """
+    def __init__(self, name=None):
+        Record.__init__(self, layout=[("applydim" , 2),
+                                      ("offset"   , 6),
+                                      ("invxyz"   , 3),
+                                      ("permute"  , 3),
+                                      ("zdimsz"   , 6),
+                                      ("ydimsz"   , 6),
+                                      ("xdimsz"   , 6)], name=name)
+
+    def ports(self):
+        return [self.applydim, self.offset, self.invxyz, self.permute,
+                self.zdimsz, self.ydimsz, self.xdimsz]