From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 19 Mar 2020 02:58:38 +0000 (+0000)
Subject: invert bits of field in decoder (not instruction bits)
X-Git-Tag: div_pipeline~1680
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8554f1dff89cf76e4da64a483e6997daf8e4f2e6;p=soc.git

invert bits of field in decoder (not instruction bits)
---

diff --git a/src/soc/decoder/power_fieldsn.py b/src/soc/decoder/power_fieldsn.py
index fdba7c05..19d37102 100644
--- a/src/soc/decoder/power_fieldsn.py
+++ b/src/soc/decoder/power_fieldsn.py
@@ -28,16 +28,20 @@ class SignalBitRange(BitRange):
             if stop is None:
                 stop = -1
             if start < 0:
-                start = len(self) - start - 1
+                start = len(self) + start
             if stop < 0:
-                stop = len(self) - stop - 1
+                stop = len(self) + stop
             print ("range", start, stop, step)
             for t in range(start, stop, step):
+                t = len(self) - 1 - t # invert field back
                 k = OrderedDict.__getitem__(self, t)
                 print ("t", t, k)
                 res.append(self.signal[self._rev(k)]) # reverse-order here
             return Cat(*res)
         else:
+            if subs < 0:
+                subs = len(self) + sub
+            subs = len(self) - 1 - subs # invert field back
             k = OrderedDict.__getitem__(self, subs)
             return self.signal[self._rev(k)] # reverse-order here