From: Staf Verhaegen Date: Fri, 8 May 2020 11:10:52 +0000 (+0200) Subject: Re: [libre-riscv-dev] minimum viable ASIC X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=855f81fbcfb8f473cb2a0b052222ea573c38cf16;p=libre-riscv-dev.git Re: [libre-riscv-dev] minimum viable ASIC --- diff --git a/5c/b0f8c05b11061b976080b7098d311857ac4e23 b/5c/b0f8c05b11061b976080b7098d311857ac4e23 new file mode 100644 index 0000000..19bad0f --- /dev/null +++ b/5c/b0f8c05b11061b976080b7098d311857ac4e23 @@ -0,0 +1,89 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Fri, 08 May 2020 12:10:58 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jX0u9-0001CC-ON; Fri, 08 May 2020 12:10:57 +0100 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) id 1jX0u9-0001C6-2n + for libre-riscv-dev@lists.libre-riscv.org; Fri, 08 May 2020 12:10:57 +0100 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id CCE2A11C059A + for ; + Fri, 8 May 2020 13:10:56 +0200 (CEST) +Message-ID: <61f61ed3979b30eb8d59bfe5d352a01c8f93cd59.camel@fibraservi.eu> +From: Staf Verhaegen +To: libre-riscv-dev@lists.libre-riscv.org +Date: Fri, 08 May 2020 13:10:52 +0200 +In-Reply-To: +References: + <7fcce2dc2715c268c1029783a83ebcd814c489b9.camel@fibraservi.eu> + +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] minimum viable ASIC +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============2402466157029274609==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============2402466157029274609== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-+6UGYYEZfJAghMunt3Hd" + + +--=-+6UGYYEZfJAghMunt3Hd +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 11:42 [+0100]: +> On Friday, May 8, 2020, Staf Verhaegen wrote: +> > Why only 24MHz without PLL ? You should have problems getting externalc= +lock frequencies up to 100MHz without a problem inside a chip. +>=20 +> really? great! and that's driven from an external 100mhz clock? it seem= +sa little high, i guess i am used to SoCs which all run from a 24mhz XTAL. + +There exist clock generator chips, some of them even programmable over a se= +rial bus interface. In the retro world amiga 75MHz accelerator cards or abo= +ve are not unheard of. +greets,Staf. + + +--=-+6UGYYEZfJAghMunt3Hd-- + + + +--===============2402466157029274609== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============2402466157029274609==-- + + +