From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Thu, 1 Aug 2019 13:45:10 +0000 (+0200)
Subject: radv: only account for tile_swizzle for color surfaces with DCC
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=856487a280f58bf2e7cf1d6a13c659375e6a3d5f;p=mesa.git

radv: only account for tile_swizzle for color surfaces with DCC

It's 0 for depth surfaces with TC compat HTILE enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index f3237dd5985..221b554e73e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -483,6 +483,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 			meta_va = gpu_address + image->dcc_offset;
 			if (chip_class <= GFX8)
 				meta_va += base_level_info->dcc_offset;
+
+			meta_va |= (uint32_t)plane->surface.tile_swizzle << 8;
 		} else if (!is_storage_image &&
 			   radv_image_is_tc_compat_htile(image)) {
 			meta_va = gpu_address + image->htile_offset;
@@ -490,10 +492,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 
 		if (meta_va) {
 			state[6] |= S_008F28_COMPRESSION_EN(1);
-			if (chip_class <= GFX9) {
+			if (chip_class <= GFX9)
 				state[7] = meta_va >> 8;
-				state[7] |= plane->surface.tile_swizzle;
-			}
 		}
 	}