From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Aug 2022 01:35:58 +0000 (+0100)
Subject: update comments
X-Git-Tag: sv_maxu_works-initial~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=85648d40b733c2cbb405e6b1fc19c9fd4c2b0594;p=openpower-isa.git

update comments
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index d93cb826..730b00a2 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -660,12 +660,14 @@ class SVP64Asm:
         else:
             v30b_op = v30b_op_orig
 
+        # look up the 32-bit op (original, with "," if it has it)
         if v30b_op_orig not in isa.instr:
             raise Exception("opcode %s of '%s' not supported" %
                             (v30b_op_orig, insn))
         else:
             isa_instr = isa.instr[v30b_op_orig]
 
+        # look up the svp64 op
         if v30b_op_orig not in svp64.instrs:
             if v30b_op in svp64.instrs:
                 rm = svp64.instrs[v30b_op]  # one row of the svp64 RM CSV
@@ -674,7 +676,9 @@ class SVP64Asm:
                                 f"{insn!r} not an svp64 instruction")
         else:
             rm = svp64.instrs[v30b_op_orig]  # one row of the svp64 RM CSV
-        v30b_regs = isa_instr.regs[0]  # get regs info "RT, RA, RB"
+
+        # get regs info e.g. "RT,RA,RB"
+        v30b_regs = isa_instr.regs[0]
         log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
         log("v3.0B regs", opcode, v30b_regs)
         log("RM", rm)